Lines Matching defs:dp
85 static int rockchip_edp_phy_set_voltages(struct rockchip_edp_phy *edpphy, struct phy_configure_opts_dp *dp)
90 for (lane = 0; lane < dp->lanes; lane++) {
91 val = vp[dp->voltage[lane]][dp->pre[lane]].amp;
94 val = vp[dp->voltage[lane]][dp->pre[lane]].amp_scale;
97 val = vp[dp->voltage[lane]][dp->pre[lane]].emp;
104 static int rockchip_edp_phy_set_rate(struct rockchip_edp_phy *edpphy, struct phy_configure_opts_dp *dp)
114 switch (dp->link_rate) {
129 if (dp->ssc) {
136 writel(EDP_PHY_TX_PD(~GENMASK(dp->lanes - 1, 0)), edpphy->regs + EDP_PHY_GRF_CON0);
144 writel(EDP_PHY_TX_IDLE(~GENMASK(dp->lanes - 1, 0)), edpphy->regs + EDP_PHY_GRF_CON0);
149 static int rockchip_edp_phy_verify_config(struct rockchip_edp_phy *edpphy, struct phy_configure_opts_dp *dp)
154 if (dp->set_rate) {
155 switch (dp->link_rate) {
166 switch (dp->lanes) {
180 if (dp->set_voltages) {
182 for (i = 0; i < dp->lanes; i++) {
183 if (dp->voltage[i] > 0x03 || dp->pre[i] > 0x03) {
191 if (dp->voltage[i] + dp->pre[i] > 0x03) {
205 ret = rockchip_edp_phy_verify_config(edpphy, &opts->dp);
211 if (opts->dp.set_rate) {
212 ret = rockchip_edp_phy_set_rate(edpphy, &opts->dp);
219 if (opts->dp.set_voltages) {
220 ret = rockchip_edp_phy_set_voltages(edpphy, &opts->dp);