Lines Matching refs:priv
73 int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
117 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
119 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
124 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
130 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv)
135 if (priv->cfg->combphy_cfg) {
136 ret = priv->cfg->combphy_cfg(priv);
138 dev_err(priv->dev, "failed to init phy for pcie\n");
143 if (priv->cfg->force_det_out) {
144 val = readl(priv->mmio + (0x19 << 0x02));
146 writel(val, priv->mmio + (0x19 << 0x02));
152 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv)
156 if (priv->cfg->combphy_cfg) {
157 ret = priv->cfg->combphy_cfg(priv);
159 dev_err(priv->dev, "failed to init phy for usb3\n");
167 static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv)
171 if (priv->cfg->combphy_cfg) {
172 ret = priv->cfg->combphy_cfg(priv);
174 dev_err(priv->dev, "failed to init phy for sata\n");
182 static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv)
186 if (priv->cfg->combphy_cfg) {
187 ret = priv->cfg->combphy_cfg(priv);
189 dev_err(priv->dev, "failed to init phy for sgmii\n");
197 static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv)
199 switch (priv->mode) {
201 rockchip_combphy_pcie_init(priv);
204 rockchip_combphy_usb3_init(priv);
207 rockchip_combphy_sata_init(priv);
211 return rockchip_combphy_sgmii_init(priv);
213 dev_err(priv->dev, "incompatible PHY type\n");
222 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
223 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
227 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
229 dev_err(priv->dev, "failed to enable clks\n");
233 ret = rockchip_combphy_set_mode(priv);
238 ret = reset_control_deassert(priv->phy_rst);
243 if (priv->mode == PHY_TYPE_USB3) {
244 ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready, priv, val, val == cfg->pipe_phy_status.enable, 0xA,
247 dev_warn(priv->dev, "wait phy status ready timeout\n");
254 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
261 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
263 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
264 reset_control_assert(priv->phy_rst);
277 struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
284 if (priv->mode != PHY_NONE && priv->mode != args->args[0]) {
285 dev_warn(dev, "phy type select %d overwriting type %d\n", args->args[0], priv->mode);
288 priv->mode = args->args[0];
290 return priv->phy;
293 static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
295 const struct rockchip_combphy_cfg *phy_cfg = priv->cfg;
299 ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
304 priv->num_clks = 0;
307 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
308 if (IS_ERR(priv->pipe_grf)) {
310 return PTR_ERR(priv->pipe_grf);
313 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
314 if (IS_ERR(priv->phy_grf)) {
316 return PTR_ERR(priv->phy_grf);
320 param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en, false);
322 param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en, false);
326 param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, true);
330 regmap_write(priv->pipe_grf, vals[0], (GENMASK(vals[0x02], vals[1]) << 0x10) | (vals[0x03] << vals[1]));
333 priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb");
334 if (IS_ERR(priv->apb_rst)) {
335 ret = PTR_ERR(priv->apb_rst);
343 priv->phy_rst = devm_reset_control_get_optional(dev, "combphy");
344 if (IS_ERR(priv->phy_rst)) {
345 ret = PTR_ERR(priv->phy_rst);
353 return reset_control_assert(priv->phy_rst);
360 struct rockchip_combphy_priv *priv;
371 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
372 if (!priv) {
377 priv->mmio = devm_ioremap_resource(dev, res);
378 if (IS_ERR(priv->mmio)) {
379 ret = PTR_ERR(priv->mmio);
383 priv->num_clks = phy_cfg->num_clks;
385 priv->clks = devm_kmemdup(dev, phy_cfg->clks, phy_cfg->num_clks * sizeof(struct clk_bulk_data), GFP_KERNEL);
387 if (!priv->clks) {
391 priv->dev = dev;
392 priv->mode = PHY_NONE;
393 priv->cfg = phy_cfg;
395 ret = rockchip_combphy_parse_dt(dev, priv);
400 priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
401 if (IS_ERR(priv->phy)) {
403 return PTR_ERR(priv->phy);
406 dev_set_drvdata(dev, priv);
407 phy_set_drvdata(priv->phy, priv);
414 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
416 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
423 for (i = 0; i < priv->num_clks; i++) {
424 if (!strncmp(priv->clks[i].id, "refclk", 0x6)) {
425 refclk = priv->clks[i].clk;
431 dev_err(priv->dev, "No refclk found\n");
435 switch (priv->mode) {
438 val = readl(priv->mmio + (0x1f << 0x02));
441 writel(val, priv->mmio + 0x7c);
443 param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
444 param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
445 param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
446 param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
450 val = readl(priv->mmio + (0x1f << 0x02));
453 writel(val, priv->mmio + 0x7c);
456 val = readl(priv->mmio + (0x0e << 0x02));
459 writel(val, priv->mmio + (0x0e << 0x02));
462 val = readl(priv->mmio + (0x20 << 0x02));
465 writel(val, priv->mmio + (0x20 << 0x02));
468 writel(0x4, priv->mmio + (0xb << 0x02));
471 val = readl(priv->mmio + (0x5 << 2));
474 writel(val, priv->mmio + (0x5 << 0x02));
477 writel(0x32, priv->mmio + (0x11 << 0x02));
480 writel(0xf0, priv->mmio + (0xa << 0x02));
482 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
483 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
484 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
485 param_write(priv->phy_grf, &cfg->usb_mode_set, true);
488 writel(0x41, priv->mmio + 0x38);
489 writel(0x8F, priv->mmio + 0x18);
490 param_write(priv->phy_grf, &cfg->con0_for_sata, true);
491 param_write(priv->phy_grf, &cfg->con1_for_sata, true);
492 param_write(priv->phy_grf, &cfg->con2_for_sata, true);
493 param_write(priv->phy_grf, &cfg->con3_for_sata, true);
494 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
497 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
498 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
499 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
500 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
503 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
504 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
505 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
506 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
507 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
510 dev_err(priv->dev, "incompatible PHY type\n");
518 if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) {
520 val = readl(priv->mmio + (0x0e << 0x02));
523 writel(val, priv->mmio + (0x0e << 0x02));
525 val = readl(priv->mmio + (0x0f << 0x02));
528 writel(val, priv->mmio + (0x0f << 0x02));
532 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
535 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
536 if (priv->mode == PHY_TYPE_PCIE) {
538 val = readl(priv->mmio + (0x20 << 0x02));
541 writel(val, priv->mmio + (0x20 << 0x02));
544 writel(0x4, priv->mmio + (0xb << 0x02));
546 val = readl(priv->mmio + (0x5 << 0x02));
549 writel(val, priv->mmio + (0x5 << 0x02));
551 writel(0x32, priv->mmio + (0x11 << 0x02));
552 writel(0xf0, priv->mmio + (0xa << 0x02));
553 } else if (priv->mode == PHY_TYPE_SATA) {
555 val = readl(priv->mmio + (0x1f << 0x02));
558 writel(val, priv->mmio + (0x1f << 0x02));
562 dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
566 if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
567 param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
568 if (priv->mode == PHY_TYPE_PCIE && rate == 0x5F5E100) {
569 val = readl(priv->mmio + (0xc << 0x02));
571 writel(val, priv->mmio + (0xc << 0x02));
573 val = readl(priv->mmio + (0xd << 0x02));
575 writel(val, priv->mmio + (0xd << 0x02));
579 if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
580 val = readl(priv->mmio + (0x7 << 0x02));
582 writel(val, priv->mmio + (0x7 << 0x02));
638 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
640 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
647 for (i = 0; i < priv->num_clks; i++) {
648 if (!strncmp(priv->clks[i].id, "refclk", 0x06)) {
649 refclk = priv->clks[i].clk;
655 dev_err(priv->dev, "No refclk found\n");
659 switch (priv->mode) {
661 param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
662 param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
663 param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
664 param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
668 val = readl(priv->mmio + (0x1f << 0x02));
671 writel(val, priv->mmio + 0x7c);
674 val = readl(priv->mmio + (0x0e << 0x02));
677 writel(val, priv->mmio + (0x0e << 0x02));
680 val = readl(priv->mmio + (0x20 << 0x02));
683 writel(val, priv->mmio + (0x20 << 0x02));
686 writel(0x4, priv->mmio + (0xb << 0x02));
689 val = readl(priv->mmio + (0x5 << 2));
692 writel(val, priv->mmio + (0x5 << 0x02));
695 writel(0x32, priv->mmio + (0x11 << 0x02));
698 writel(0xf0, priv->mmio + (0xa << 0x02));
700 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
701 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
702 param_write(priv->phy_grf, &cfg->usb_mode_set, true);
706 val = readl(priv->mmio + (0x0e << 0x02));
709 writel(val, priv->mmio + (0x0e << 0x02));
711 writel(0x8F, priv->mmio + (0x06 << 0x02));
713 param_write(priv->phy_grf, &cfg->con0_for_sata, true);
714 param_write(priv->phy_grf, &cfg->con1_for_sata, true);
715 param_write(priv->phy_grf, &cfg->con2_for_sata, true);
716 param_write(priv->phy_grf, &cfg->con3_for_sata, true);
717 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
718 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
723 dev_err(priv->dev, "incompatible PHY type\n");
731 if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) {
733 val = readl(priv->mmio + (0x0e << 0x02));
736 writel(val, priv->mmio + (0x0e << 0x02));
738 val = readl(priv->mmio + (0x0f << 0x02));
741 writel(val, priv->mmio + (0x0f << 0x02));
745 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
748 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
749 if (priv->mode == PHY_TYPE_PCIE) {
751 val = readl(priv->mmio + (0x20 << 0x02));
754 writel(val, priv->mmio + (0x20 << 0x02));
758 writel(val, priv->mmio + (0x1b << 0x02));
762 writel(val, priv->mmio + (0xa << 0x02));
764 writel(val, priv->mmio + (0xb << 0x02));
765 } else if (priv->mode == PHY_TYPE_SATA) {
767 val = readl(priv->mmio + (0x1f << 0x02));
770 writel(val, priv->mmio + (0x1f << 0x02));
774 dev_err(priv->dev, "Unsupported rate: %lu\n", rate);