Lines Matching refs:priv
504 void (*individual_init)(struct mipidphy_priv *priv);
543 int (*stream_on)(struct mipidphy_priv *priv, struct v4l2_subdev *sd);
544 int (*stream_off)(struct mipidphy_priv *priv, struct v4l2_subdev *sd);
552 static inline void write_grf_reg(struct mipidphy_priv *priv, int index, u8 value)
554 const struct dphy_reg *reg = &priv->grf_regs[index];
558 regmap_write(priv->regmap_grf, reg->offset, val);
562 static inline u32 read_grf_reg(struct mipidphy_priv *priv, int index)
564 const struct dphy_reg *reg = &priv->grf_regs[index];
568 regmap_read(priv->regmap_grf, reg->offset, &val);
574 static inline void write_txrx_reg(struct mipidphy_priv *priv, int index, u32 value)
576 const struct txrx_reg *reg = &priv->txrx_regs[index];
579 writel(value, priv->txrx_base_addr + reg->offset);
583 static void mipidphy0_wr_reg(struct mipidphy_priv *priv, u8 test_code, u8 test_data)
590 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
591 write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_code);
592 write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 1);
593 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 0);
594 write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 0);
595 write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_data);
596 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
599 static void mipidphy1_wr_reg(struct mipidphy_priv *priv, unsigned char addr, unsigned char data)
607 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL1, PHY_TESTEN_ADDR | addr);
608 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, 0x00);
609 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL1, PHY_TESTEN_DATA | data);
610 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, 0x02);
613 static inline void write_csiphy_reg(struct mipidphy_priv *priv, int index, u32 value)
615 const struct csiphy_reg *reg = &priv->csiphy_regs[index];
618 writel(value, priv->csihost_base_addr + reg->offset);
622 static inline void read_csiphy_reg(struct mipidphy_priv *priv, int index, u32 *value)
624 const struct csiphy_reg *reg = &priv->csiphy_regs[index];
627 *value = readl(priv->csihost_base_addr + reg->offset);
631 static void csi_mipidphy_wr_ths_settle(struct mipidphy_priv *priv, int hsfreq, enum mipi_dphy_lane lane)
656 read_csiphy_reg(priv, offset, &val);
658 write_csiphy_reg(priv, offset, val);
677 static struct mipidphy_sensor *sd_to_sensor(struct mipidphy_priv *priv, struct v4l2_subdev *sd)
681 for (i = 0; i < priv->num_sensors; ++i) {
682 if (priv->sensors[i].sd == sd) {
683 return &priv->sensors[i];
692 struct mipidphy_priv *priv = to_dphy_priv(sd);
717 priv->data_rate_mbps = qm.value * 0x02;
718 do_div(priv->data_rate_mbps, 0x3E8 * 0x3E8);
719 v4l2_info(sd, "data_rate_mbps %lld\n", priv->data_rate_mbps);
725 struct mipidphy_priv *priv = to_dphy_priv(sd);
727 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
759 struct mipidphy_priv *priv = to_dphy_priv(sd);
764 oldval = read_grf_reg(priv, GRF_DPHY_SEL);
767 if (priv->phy_index == 0) {
773 if (priv->phy_index == 0) {
779 if (priv->phy_index == 0) {
787 write_grf_reg(priv, GRF_DPHY_SEL, newval);
793 struct mipidphy_priv *priv = to_dphy_priv(sd);
796 if (priv->is_streaming) {
805 if (priv->drv_data->chip_id == CHIP_ID_RK1126) {
810 priv->stream_on(priv, sd);
812 priv->is_streaming = true;
819 struct mipidphy_priv *priv = to_dphy_priv(sd);
821 if (!priv->is_streaming) {
825 if (priv->stream_off) {
826 priv->stream_off(priv, sd);
828 priv->is_streaming = false;
836 struct mipidphy_priv *priv = to_dphy_priv(sd);
838 dev_info(priv->dev, "stream on:%d\n", on);
839 mutex_lock(&priv->mutex);
845 mutex_unlock(&priv->mutex);
862 struct mipidphy_priv *priv = to_dphy_priv(sd);
869 sensor = sd_to_sensor(priv, sensor_sd);
878 struct mipidphy_priv *priv = to_dphy_priv(sd);
881 return pm_runtime_get_sync(priv->dev);
883 return pm_runtime_put(priv->dev);
891 struct mipidphy_priv *priv = to_dphy_priv(sd);
894 num_clks = priv->drv_data->num_clks;
896 if (!IS_ERR(priv->clks[i])) {
897 clk_disable_unprepare(priv->clks[i]);
908 struct mipidphy_priv *priv = to_dphy_priv(sd);
911 num_clks = priv->drv_data->num_clks;
913 if (!IS_ERR(priv->clks[i])) {
914 ret = clk_prepare_enable(priv->clks[i]);
924 clk_disable_unprepare(priv->clks[i]);
933 struct mipidphy_priv *priv = to_dphy_priv(sd);
935 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
1036 static void default_mipidphy_individual_init(struct mipidphy_priv *priv)
1040 static void rk3368_mipidphy_individual_init(struct mipidphy_priv *priv)
1043 write_grf_reg(priv, GRF_ISP_MIPI_CSI_HOST_SEL, 1);
1046 static void rk3399_mipidphy_individual_init(struct mipidphy_priv *priv)
1052 write_grf_reg(priv, GRF_DPHY_TX1RX1_SRC_SEL, 0);
1053 write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0);
1054 write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 0);
1056 write_grf_reg(priv, GRF_DVP_V18SEL, 0x1);
1059 static void rv1126_mipidphy_individual_init(struct mipidphy_priv *priv)
1061 struct device *dev = priv->dev;
1066 priv->grf_regs = priv->phy_index ? rv1126_grf_dphy1_regs : rv1126_grf_dphy0_regs;
1067 val = read_grf_reg(priv, GRF_DPHY_SEL);
1072 sel = !priv->phy_index ? 0 : RV1126_GRF_PHY1_SEL_ISP;
1074 sel = !priv->phy_index ? 0 : RV1126_GRF_PHY1_SEL_CIF | RV1126_GRF_PHY1_SEL_CIFLITE;
1077 write_grf_reg(priv, GRF_DPHY_SEL, val | sel);
1081 static int mipidphy_rx_stream_on(struct mipidphy_priv *priv, struct v4l2_subdev *sd)
1084 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
1085 const struct dphy_drv_data *drv_data = priv->drv_data;
1091 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
1099 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps", priv->data_rate_mbps,
1105 write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 0);
1113 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
1114 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 1);
1130 write_grf_reg(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf);
1131 write_grf_reg(priv, GRF_DPHY_RX0_FORCERXMODE, 0);
1132 write_grf_reg(priv, GRF_DPHY_RX0_TURNREQUEST, 0);
1136 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 0);
1145 mipidphy0_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
1146 mipidphy0_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq);
1147 mipidphy0_wr_reg(priv, LANE1_HS_RX_CONTROL, hsfreq);
1148 mipidphy0_wr_reg(priv, LANE2_HS_RX_CONTROL, hsfreq);
1149 mipidphy0_wr_reg(priv, LANE3_HS_RX_CONTROL, hsfreq);
1155 write_grf_reg(priv, GRF_DPHY_RX0_ENABLE, GENMASK(sensor->lanes - 1, 0));
1171 static int mipidphy_txrx_stream_on(struct mipidphy_priv *priv, struct v4l2_subdev *sd)
1174 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
1175 const struct dphy_drv_data *drv_data = priv->drv_data;
1181 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
1189 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps", priv->data_rate_mbps,
1200 write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 1);
1201 write_grf_reg(priv, GRF_DSI_CSI_TESTBUS_SEL, 1);
1202 write_grf_reg(priv, GRF_DPHY_RX1_SRC_SEL, 1);
1208 write_grf_reg(priv, GRF_DPHY_TX1RX1_SRC_SEL, 0);
1216 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, PHY_TESTCLR | PHY_TESTCLK);
1227 write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0);
1233 write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 1);
1236 write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCERXMODE, 0);
1237 write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCETXSTOPMODE, 0);
1238 write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNREQUEST, 0);
1239 write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNDISABLE, 0xf);
1243 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, PHY_TESTCLK);
1252 mipidphy1_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
1253 mipidphy1_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq);
1254 mipidphy1_wr_reg(priv, LANE1_HS_RX_CONTROL, 0);
1255 mipidphy1_wr_reg(priv, LANE2_HS_RX_CONTROL, 0);
1256 mipidphy1_wr_reg(priv, LANE3_HS_RX_CONTROL, 0);
1269 write_grf_reg(priv, GRF_DPHY_TX1RX1_ENABLE, GENMASK(sensor->lanes - 1, 0));
1288 static int csi_mipidphy_stream_on(struct mipidphy_priv *priv, struct v4l2_subdev *sd)
1291 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
1292 const struct dphy_drv_data *drv_data = priv->drv_data;
1298 write_grf_reg(priv, GRF_DVP_V18SEL, 0x1);
1301 write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe4);
1304 write_csiphy_reg(priv, CSIPHY_CTRL_LANE_ENABLE,
1309 write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe0);
1314 write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1e);
1315 write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1f);
1318 write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x3e);
1320 write_csiphy_reg(priv, CSIPHY_MIPI_LVDS_MODEL, 0x4);
1340 write_csiphy_reg(priv, CSIPHY_LVDS_MODE, val);
1344 write_grf_reg(priv, GRF_DPHY_CSIPHY_FORCERXMODE, 0x0);
1347 if (priv->data_rate_mbps > 0x5DC) {
1348 write_csiphy_reg(priv, CSIPHY_CLK_CALIB_ENABLE, 0x80);
1350 write_csiphy_reg(priv, CSIPHY_LANE0_CALIB_ENABLE, 0x80);
1353 write_csiphy_reg(priv, CSIPHY_LANE1_CALIB_ENABLE, 0x80);
1356 write_csiphy_reg(priv, CSIPHY_LANE2_CALIB_ENABLE, 0x80);
1359 write_csiphy_reg(priv, CSIPHY_LANE3_CALIB_ENABLE, 0x80);
1365 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
1373 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps", priv->data_rate_mbps,
1378 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_CLOCK);
1380 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA0);
1383 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA1);
1386 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA2);
1389 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA3);
1392 write_grf_reg(priv, GRF_DPHY_CLK_INV_SEL, 0x1);
1393 write_grf_reg(priv, GRF_DPHY_CSIPHY_CLKLANE_EN, 0x1);
1394 write_grf_reg(priv, GRF_DPHY_CSIPHY_DATALANE_EN, GENMASK(sensor->lanes - 1, 0));
1398 static int csi_mipidphy_stream_off(struct mipidphy_priv *priv, struct v4l2_subdev *sd)
1401 write_csiphy_reg(priv, CSIPHY_CTRL_LANE_ENABLE, 0x01);
1403 write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe3);
1506 struct mipidphy_priv *priv = container_of(notifier, struct mipidphy_priv, notifier);
1511 if (priv->num_sensors == ARRAY_SIZE(priv->sensors)) {
1515 sensor = &priv->sensors[priv->num_sensors++];
1519 dev_info(priv->dev, "match %s:bus type %d\n", sd->name, s_asd->mbus.type);
1528 dev_err(priv->dev, "failed to find src pad for %s\n", sensor->sd->name);
1533 ret = media_create_pad_link(&sensor->sd->entity, pad, &priv->sd.entity, MIPI_DPHY_RX_PAD_SINK,
1534 priv->num_sensors != 1 ? 0 : MEDIA_LNK_FL_ENABLED);
1536 dev_err(priv->dev, "failed to create link for %s\n", sensor->sd->name);
1547 struct mipidphy_priv *priv = container_of(notifier, struct mipidphy_priv, notifier);
1548 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sd);
1602 static int rockchip_mipidphy_media_init(struct mipidphy_priv *priv)
1606 priv->pads[MIPI_DPHY_RX_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
1607 priv->pads[MIPI_DPHY_RX_PAD_SINK].flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
1608 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1609 ret = media_entity_pads_init(&priv->sd.entity, MIPI_DPHY_RX_PADS_NUM, priv->pads);
1614 v4l2_async_notifier_init(&priv->notifier);
1617 priv->dev, &priv->notifier, sizeof(struct sensor_async_subdev), 0, rockchip_mipidphy_fwnode_parse);
1622 priv->sd.subdev_notifier = &priv->notifier;
1623 priv->notifier.ops = &rockchip_mipidphy_async_ops;
1624 ret = v4l2_async_subdev_notifier_register(&priv->sd, &priv->notifier);
1626 dev_err(priv->dev, "failed to register async notifier : %d\n", ret);
1627 v4l2_async_notifier_cleanup(&priv->notifier);
1631 return v4l2_async_register_subdev(&priv->sd);
1638 struct mipidphy_priv *priv;
1645 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1646 if (!priv) {
1649 priv->dev = dev;
1664 priv->regmap_grf = grf;
1666 priv->phy_index = of_alias_get_id(dev->of_node, "dphy");
1667 if (priv->phy_index < 0) {
1668 priv->phy_index = 0;
1673 priv->clks[i] = devm_clk_get(dev, drv_data->clks[i]);
1675 if (IS_ERR(priv->clks[i])) {
1680 priv->grf_regs = drv_data->grf_regs;
1681 priv->txrx_regs = drv_data->txrx_regs;
1682 priv->csiphy_regs = drv_data->csiphy_regs;
1683 priv->drv_data = drv_data;
1686 priv->csihost_base_addr = devm_ioremap_resource(dev, res);
1687 priv->stream_on = csi_mipidphy_stream_on;
1688 priv->stream_off = csi_mipidphy_stream_off;
1690 priv->stream_on = mipidphy_txrx_stream_on;
1691 priv->txrx_base_addr = NULL;
1693 priv->txrx_base_addr = devm_ioremap_resource(dev, res);
1694 if (IS_ERR(priv->txrx_base_addr)) {
1695 priv->stream_on = mipidphy_rx_stream_on;
1697 priv->stream_off = NULL;
1700 sd = &priv->sd;
1701 mutex_init(&priv->mutex);
1709 ret = rockchip_mipidphy_media_init(priv);
1715 drv_data->individual_init(priv);
1719 mutex_destroy(&priv->mutex);
1727 struct mipidphy_priv *priv = platform_get_drvdata(pdev);
1732 mutex_destroy(&priv->mutex);