Lines Matching refs:u3phy
180 static int rockchip_set_vbus_power(struct rockchip_u3phy *u3phy, bool en)
184 if (!u3phy->vbus) {
188 if (en && !u3phy->vbus_enabled) {
189 ret = regulator_enable(u3phy->vbus);
191 dev_err(u3phy->dev, "Failed to enable VBUS supply\n");
193 } else if (!en && u3phy->vbus_enabled) {
194 ret = regulator_disable(u3phy->vbus);
198 u3phy->vbus_enabled = en;
206 struct rockchip_u3phy *u3phy = s->private;
208 if (param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) {
209 dev_info(u3phy->dev, "u2\n");
211 dev_info(u3phy->dev, "u3\n");
225 struct rockchip_u3phy *u3phy = s->private;
234 if (!strncmp(buf, "u3", 2) && param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) {
235 dev_info(u3phy->dev, "Set usb3.0 and usb2.0 mode successfully\n");
237 rockchip_set_vbus_power(u3phy, false);
239 param_write(u3phy->grf, &u3phy->cfgs->grfcfg.u3_disable, false);
240 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, false);
243 u3phy_port = &u3phy->ports[index];
250 atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL);
252 rockchip_set_vbus_power(u3phy, true);
253 } else if (!strncmp(buf, "u2", 2) && param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, 0)) {
254 dev_info(u3phy->dev, "Set usb2.0 only mode successfully\n");
256 rockchip_set_vbus_power(u3phy, false);
258 param_write(u3phy->grf, &u3phy->cfgs->grfcfg.u3_disable, true);
259 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, true);
262 u3phy_port = &u3phy->ports[index];
269 atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL);
271 rockchip_set_vbus_power(u3phy, true);
273 dev_info(u3phy->dev, "Same or illegal mode\n");
287 int rockchip_u3phy_debugfs_init(struct rockchip_u3phy *u3phy)
293 root = debugfs_create_dir(dev_name(u3phy->dev), NULL);
299 u3phy->root = root;
301 file = debugfs_create_file("u3phy_mode", FILE_RIGHT_644, root, u3phy, &rockchip_u3phy_usb2_only_fops);
318 return "u3phy-u2-por";
320 return "u3phy-u3-por";
322 return "u3phy-pipe-mac";
324 return "u3phy-utmi-mac";
326 return "u3phy-utmi-apb";
328 return "u3phy-pipe-apb";
334 static void rockchip_u3phy_rest_deassert(struct rockchip_u3phy *u3phy, unsigned int flag)
339 dev_dbg(u3phy->dev, "deassert APB bus interface reset\n");
341 if (u3phy->rsts[rst]) {
342 reset_control_deassert(u3phy->rsts[rst]);
349 dev_dbg(u3phy->dev, "deassert u2 and u3 phy power on reset\n");
351 if (u3phy->rsts[rst]) {
352 reset_control_deassert(u3phy->rsts[rst]);
359 dev_dbg(u3phy->dev, "deassert pipe and utmi MAC reset\n");
361 if (u3phy->rsts[rst]) {
362 reset_control_deassert(u3phy->rsts[rst]);
368 static void rockchip_u3phy_rest_assert(struct rockchip_u3phy *u3phy)
372 dev_dbg(u3phy->dev, "assert u3phy reset\n");
374 if (u3phy->rsts[rst]) {
375 reset_control_assert(u3phy->rsts[rst]);
380 static int rockchip_u3phy_clk_enable(struct rockchip_u3phy *u3phy)
384 for (clk = 0; clk < U3PHY_MAX_CLKS && u3phy->clks[clk]; clk++) {
385 ret = clk_prepare_enable(u3phy->clks[clk]);
394 clk_disable_unprepare(u3phy->clks[clk]);
399 static void rockchip_u3phy_clk_disable(struct rockchip_u3phy *u3phy)
404 if (u3phy->clks[clk]) {
405 clk_disable_unprepare(u3phy->clks[clk]);
423 struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
426 dev_info(&u3phy_port->phy->dev, "u3phy %s power on\n", (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3");
432 ret = rockchip_u3phy_clk_enable(u3phy);
438 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.um_suspend, false);
441 if (param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P2)) {
445 if (u3phy->cfgs->phy_pipe_power) {
446 dev_dbg(u3phy->dev, "do pipe power up\n");
447 u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, true);
451 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true);
455 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P2], false);
460 rockchip_set_vbus_power(u3phy, true);
468 struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
470 dev_info(&u3phy_port->phy->dev, "u3phy %s power off\n", (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3");
477 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.um_suspend, true);
480 if (param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P3)) {
485 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true);
489 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P3], true);
492 if (u3phy->cfgs->phy_pipe_power) {
493 dev_dbg(u3phy->dev, "do pipe power down\n");
494 u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, false);
499 rockchip_u3phy_clk_disable(u3phy);
506 struct rockchip_u3phy *u3phy = dev_get_drvdata(dev);
517 if (phy_np == u3phy->ports[index].phy->dev.of_node) {
518 u3phy_port = &u3phy->ports[index];
552 struct rockchip_u3phy *u3phy = dev_get_drvdata(u3phy_port->phy->dev.parent);
553 unsigned int sh = u3phy->cfgs->grfcfg.um_hstdct.bitend - u3phy->cfgs->grfcfg.um_hstdct.bitstart + 1;
560 ret = regmap_read(u3phy->u3phy_grf, u3phy->cfgs->grfcfg.um_ls.offset, &ul);
565 ret = regmap_read(u3phy->u3phy_grf, u3phy->cfgs->grfcfg.um_hstdct.offset, &uhd);
570 uhd_mask = GENMASK(u3phy->cfgs->grfcfg.um_hstdct.bitend, u3phy->cfgs->grfcfg.um_hstdct.bitstart);
571 ul_mask = GENMASK(u3phy->cfgs->grfcfg.um_ls.bitend, u3phy->cfgs->grfcfg.um_ls.bitstart);
574 state = ((uhd & uhd_mask) >> u3phy->cfgs->grfcfg.um_hstdct.bitstart) |
575 (((ul & ul_mask) >> u3phy->cfgs->grfcfg.um_ls.bitstart) << sh);
618 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_st, true);
619 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_en, true);
640 struct rockchip_u3phy *u3phy = dev_get_drvdata(u3phy_port->phy->dev.parent);
642 if (!param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_st, u3phy->cfgs->grfcfg.ls_det_st.dvalue)) {
646 dev_dbg(u3phy->dev, "utmi linestate interrupt\n");
650 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_en, false);
651 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_st, true);
661 dev_dbg(u3phy->dev, "schedule utmi sm work\n");
668 static int rockchip_u3phy_parse_dt(struct rockchip_u3phy *u3phy, struct platform_device *pdev)
675 u3phy->um_ls_irq = platform_get_irq_byname(pdev, "linestate");
676 if (u3phy->um_ls_irq < 0) {
682 u3phy->vbus = devm_regulator_get_optional(dev, "vbus");
683 if (IS_ERR(u3phy->vbus)) {
684 ret = PTR_ERR(u3phy->vbus);
690 u3phy->vbus = NULL;
694 u3phy->clks[clk] = of_clk_get(np, clk);
695 if (IS_ERR(u3phy->clks[clk])) {
696 ret = PTR_ERR(u3phy->clks[clk]);
700 u3phy->clks[clk] = NULL;
706 u3phy->rsts[i] = devm_reset_control_get(dev, get_rest_name(i));
707 if (IS_ERR(u3phy->rsts[i])) {
709 u3phy->rsts[i] = NULL;
717 clk_put(u3phy->clks[clk]);
722 static int rockchip_u3phy_port_init(struct rockchip_u3phy *u3phy, struct rockchip_u3phy_port *u3phy_port,
729 dev_dbg(u3phy->dev, "u3phy port initialize\n");
734 phy = devm_phy_create(u3phy->dev, child_np, &rockchip_u3phy_ops);
736 dev_err(u3phy->dev, "failed to create phy\n");
744 dev_err(u3phy->dev, "failed to get address resource(np-%s)\n", child_np->name);
750 dev_err(u3phy->dev, "failed to remap phy regs\n");
761 ret = devm_request_threaded_irq(u3phy->dev, u3phy->um_ls_irq, NULL, rockchip_u3phy_um_ls_irq, IRQF_ONESHOT,
764 dev_err(u3phy->dev, "failed to request utmi linestate irq handle\n");
769 if (u3phy->cfgs->phy_tuning) {
770 dev_dbg(u3phy->dev, "do u3phy tuning\n");
771 ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np);
783 struct rockchip_u3phy *u3phy = container_of(usb_phy, struct rockchip_u3phy, usb_phy);
785 rockchip_u3phy_rest_deassert(u3phy, U3PHY_POR_RST | U3PHY_MAC_RST);
791 struct rockchip_u3phy *u3phy = container_of(usb_phy, struct rockchip_u3phy, usb_phy);
795 if (u3phy->rsts[rst] && rst != UTMI_APB_RSTN && rst != PIPE_APB_RSTN) {
796 reset_control_assert(u3phy->rsts[rst]);
804 struct rockchip_u3phy *u3phy = container_of(usb_phy, struct rockchip_u3phy, usb_phy);
806 dev_info(u3phy->dev, "%s device has disconnected\n", (speed == USB_SPEED_SUPER) ? "U3" : "UW/U2/U1.1/U1");
821 struct rockchip_u3phy *u3phy;
833 u3phy = devm_kzalloc(dev, sizeof(*u3phy), GFP_KERNEL);
834 if (!u3phy) {
838 u3phy->u3phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,u3phygrf");
839 if (IS_ERR(u3phy->u3phy_grf)) {
840 return PTR_ERR(u3phy->u3phy_grf);
843 u3phy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
844 if (IS_ERR(u3phy->grf)) {
846 return PTR_ERR(u3phy->grf);
854 u3phy->dev = dev;
855 u3phy->vbus_enabled = false;
857 platform_set_drvdata(pdev, u3phy);
863 u3phy->cfgs = &phy_cfgs[index];
870 if (!u3phy->cfgs) {
875 ret = rockchip_u3phy_parse_dt(u3phy, pdev);
881 ret = rockchip_u3phy_clk_enable(u3phy);
887 rockchip_u3phy_rest_assert(u3phy);
888 rockchip_u3phy_rest_deassert(u3phy, U3PHY_APB_RST | U3PHY_POR_RST);
893 struct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index];
896 ret = rockchip_u3phy_port_init(u3phy, u3phy_port, child_np);
898 dev_err(dev, "u3phy port init failed,ret(%d)\n", ret);
913 rockchip_u3phy_rest_deassert(u3phy, U3PHY_MAC_RST);
914 rockchip_u3phy_clk_disable(u3phy);
916 u3phy->usb_phy.dev = dev;
917 u3phy->usb_phy.init = rockchip_u3phy_on_init;
918 u3phy->usb_phy.shutdown = rockchip_u3phy_on_shutdown;
919 u3phy->usb_phy.notify_disconnect = rockchip_u3phy_on_disconnect;
920 usb_add_phy(&u3phy->usb_phy, USB_PHY_TYPE_USB3);
921 ATOMIC_INIT_NOTIFIER_HEAD(&u3phy->usb_phy.notifier);
923 rockchip_u3phy_debugfs_init(u3phy);
925 dev_info(dev, "Rockchip u3phy initialized successfully\n");
933 static int rk3328_u3phy_pipe_power(struct rockchip_u3phy *u3phy, struct rockchip_u3phy_port *u3phy_port, bool on)
986 static int rk3328_u3phy_tuning(struct rockchip_u3phy *u3phy, struct rockchip_u3phy_port *u3phy_port,
1000 u3phy->apbcfg.u2_pre_emp = 0x0f;
1003 u3phy->apbcfg.u2_pre_emp_sth = 0x41;
1006 u3phy->apbcfg.u2_odt_tuning = 0xb5;
1008 of_property_read_u32(child_np, "rockchip,odt-val-tuning", &u3phy->apbcfg.u2_odt_tuning);
1010 writel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030);
1011 writel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040);
1012 writel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c);
1015 dev_dbg(u3phy->dev, "switch to 25m refclk\n");
1054 dev_err(u3phy->dev, "invalid u3phy port type\n");
1085 {.compatible = "rockchip,rk3328-u3phy", .data = &rk3328_u3phy_cfgs}, {}};
1092 .name = "rockchip-u3phy",