Lines Matching refs:tmdsclock
157 unsigned long tmdsclock;
183 unsigned long tmdsclock;
188 unsigned long tmdsclock;
203 unsigned long tmdsclock;
539 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock);
546 if (!tmdsclock) {
553 } else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && tmdsclock <= 0x202FBF0 && inno->efuse_flag) {
557 for (; cfg->tmdsclock != ~0UL; cfg++) {
558 if (tmdsclock <= cfg->tmdsclock && cfg->version & chipversion) {
563 for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++) {
564 if (tmdsclock <= phy_cfg->tmdsclock) {
569 if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL) {
591 inno->tmdsclock = 0;
657 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
680 for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) {
681 if (inno->phy_cfg[i].tmdsclock >= tmdsclock) {
686 if (inno->phy_cfg[i].tmdsclock == ~0UL) {
697 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
699 dev_dbg(inno->dev, "%s rate %lu tmdsclk %u\n", __func__, rate, tmdsclock);
701 if (inno->tmdsclock == tmdsclock) {
706 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock) {
721 inno->tmdsclock = tmdsclock;
844 if (cfg->tmdsclock > 0x1443FD00) {
993 if (phy_cfg->tmdsclock > 0x1443FD00) {
1003 if (phy_cfg->tmdsclock > 0x9D5B340) {
1014 do_div(temp, inno->tmdsclock);
1035 if (phy_cfg->tmdsclock > 0x1443FD00) {
1253 phy_cfg[i].tmdsclock = (unsigned long)config[i * 0x0F];
1264 phy_cfg[i].tmdsclock = ~0UL;