Lines Matching defs:inno
211 void (*init)(struct inno_hdmi_phy *inno);
212 int (*power_on)(struct inno_hdmi_phy *inno, const struct post_pll_config *cfg, const struct phy_config *phy_cfg);
213 void (*power_off)(struct inno_hdmi_phy *inno);
214 int (*pre_pll_update)(struct inno_hdmi_phy *inno, const struct pre_pll_config *cfg);
215 unsigned long (*recalc_rate)(struct inno_hdmi_phy *inno, unsigned long parent_rate);
434 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val)
436 regmap_write(inno->regmap, reg * 0x04, val);
439 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg)
443 regmap_read(inno->regmap, reg * 0x04, &val);
448 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, u8 mask, u8 val)
450 regmap_update_bits(inno->regmap, reg * 0x04, mask, val);
453 static u32 inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, int rate)
455 int bus_width = phy_get_bus_width(inno->phy);
486 struct inno_hdmi_phy *inno = dev_id;
489 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) {
493 intr_stat1 = inno_read(inno, 0x04);
494 intr_stat2 = inno_read(inno, 0x06);
495 intr_stat3 = inno_read(inno, 0x08);
498 inno_write(inno, 0x04, intr_stat1);
501 inno_write(inno, 0x06, intr_stat2);
504 inno_write(inno, 0x08, intr_stat3);
516 struct inno_hdmi_phy *inno = dev_id;
518 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) {
522 inno_update_bits(inno, 0x02, 1, 0);
527 inno_update_bits(inno, 0x02, 1, 1);
536 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
538 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;
539 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock);
542 if (inno->phy_cfg) {
543 phy_cfg = inno->phy_cfg;
547 dev_err(inno->dev, "TMDS clock is zero!\n");
551 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3328 && rockchip_get_cpu_version()) {
553 } else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && tmdsclock <= 0x202FBF0 && inno->efuse_flag) {
573 dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
574 inno_hdmi_phy_clk_set_rate(&inno->hw, inno->pixclock, 0);
576 if (inno->plat_data->ops->power_on) {
577 return inno->plat_data->ops->power_on(inno, cfg, phy_cfg);
585 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
587 if (inno->plat_data->ops->power_off) {
588 inno->plat_data->ops->power_off(inno);
591 inno->tmdsclock = 0;
592 dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
605 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
608 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) {
609 status = inno_read(inno, 0xe0) & PRE_PLL_POWER_MASK;
611 status = inno_read(inno, 0xa0) & 1;
619 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
621 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) {
622 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);
624 inno_update_bits(inno, 0xa0, 1, 0);
632 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
634 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) {
635 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);
637 inno_update_bits(inno, 0xa0, 1, 1);
643 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
645 if (inno->plat_data->ops->recalc_rate) {
646 return inno->plat_data->ops->recalc_rate(inno, parent_rate);
648 return inno->pixclock;
656 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
657 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
675 if (!inno->phy_cfg) {
680 for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) {
681 if (inno->phy_cfg[i].tmdsclock >= tmdsclock) {
686 if (inno->phy_cfg[i].tmdsclock == ~0UL) {
695 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
697 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
699 dev_dbg(inno->dev, "%s rate %lu tmdsclk %u\n", __func__, rate, tmdsclock);
701 if (inno->tmdsclock == tmdsclock) {
712 dev_err(inno->dev, "unsupported rate %lu\n", rate);
716 if (inno->plat_data->ops->pre_pll_update) {
717 inno->plat_data->ops->pre_pll_update(inno, cfg);
720 inno->pixclock = rate;
721 inno->tmdsclock = tmdsclock;
735 static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
737 struct device *dev = inno->dev;
761 inno->hw.init = &init;
763 inno->pclk = devm_clk_register(dev, &inno->hw);
764 if (IS_ERR(inno->pclk)) {
765 ret = PTR_ERR(inno->pclk);
770 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->pclk);
779 static int inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno, const struct post_pll_config *cfg,
786 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_DISABLE);
789 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);
790 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN);
795 inno_update_bits(inno, 0xe9, m, v);
799 inno_update_bits(inno, 0xeb, m, v);
800 inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv));
806 inno_update_bits(inno, 0xe9, m, v);
811 inno_update_bits(inno, 0xe9, m, v);
815 inno_update_bits(inno, 0xeb, m, v);
819 inno_write(inno, 0xef + v, phy_cfg->regs[v]);
823 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_UP);
824 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);
827 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_ENABLE);
830 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_ENABLE);
834 while (!(inno_read(inno, 0xeb) & POST_PLL_LOCK_STATUS)) {
836 dev_err(inno->dev, "Post-PLL unlock\n");
849 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_ENABLE);
853 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno)
856 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_DISABLE);
859 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_DISABLE);
862 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN);
865 static void inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
878 inno_update_bits(inno, 0x01, m, v);
879 inno_update_bits(inno, 0x02, BYPASS_PDATA_EN_MASK, BYPASS_PDATA_EN);
885 if ((inno_read(inno, 0xe9) != 0xe4 || inno_read(inno, 0xea) != 0x50)) {
886 dev_info(inno->dev, "phy had been powered up\n");
887 inno->phy->power_count = 1;
889 inno_hdmi_phy_rk3228_power_off(inno);
891 inno_update_bits(inno, 0xaa, POST_PLL_CTRL_MASK, POST_PLL_CTRL_MANUAL);
894 cell = nvmem_cell_get(inno->dev, "hdmi_phy_flag");
896 dev_err(inno->dev, "failed to get id cell: %ld\n", PTR_ERR(cell));
902 inno->efuse_flag = efuse_buf[0] ? true : false;
907 static int inno_hdmi_phy_rk3228_pre_pll_update(struct inno_hdmi_phy *inno, const struct pre_pll_config *cfg)
913 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);
917 inno_update_bits(inno, 0xe2, m, v);
919 inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
923 inno_update_bits(inno, 0xe4, m, v);
927 inno_update_bits(inno, 0xe5, m, v);
932 inno_update_bits(inno, 0xe6, m, v);
935 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);
939 while (!(inno_read(inno, 0xe8) & PRE_PLL_LOCK_STATUS)) {
941 dev_err(inno->dev, "Pre-PLL unlock\n");
952 static int inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, const struct post_pll_config *cfg,
959 inno_update_bits(inno, 0x02, 1, 0);
961 inno_update_bits(inno, 0xaa, 1, 1);
964 inno_write(inno, 0xac, val);
966 inno_write(inno, 0xaa, 0x02);
968 inno_write(inno, 0xab, val);
971 inno_write(inno, 0xad, val);
973 inno_write(inno, 0xab, val);
974 inno_write(inno, 0xaa, 0x0e);
978 inno_write(inno, 0xb5 + val, phy_cfg->regs[val]);
988 inno_write(inno, 0xc8, 0);
989 inno_write(inno, 0xc9, 0);
990 inno_write(inno, 0xca, 0);
991 inno_write(inno, 0xcb, 0);
995 val = clk_get_rate(inno->sysclk) / 0x186A0;
996 inno_write(inno, 0xc5, ((val >> 0x08) & 0xff) | 0x80);
997 inno_write(inno, 0xc6, val & 0xff);
998 inno_write(inno, 0xc7, 0x03 << 1);
999 inno_write(inno, 0xc5, ((val >> 0x08) & 0xff));
1001 inno_write(inno, 0xc5, 0x81);
1004 inno_write(inno, 0xc8, 0x30);
1007 inno_write(inno, 0xc9, 0x10);
1008 inno_write(inno, 0xca, 0x10);
1009 inno_write(inno, 0xcb, 0x10);
1014 do_div(temp, inno->tmdsclock);
1015 inno_write(inno, 0xd8, (temp >> 0x08) & 0xff);
1016 inno_write(inno, 0xd9, temp & 0xff);
1019 inno_update_bits(inno, 0xaa, 1, 0);
1021 inno_update_bits(inno, 0xb0, 0x04, 0x04);
1022 inno_write(inno, 0xb2, 0x0f);
1026 if (inno_read(inno, 0xaf) & 1) {
1031 if (!(inno_read(inno, 0xaf) & 1)) {
1032 dev_err(inno->dev, "HDMI PHY Post PLL unlock\n");
1039 inno_update_bits(inno, 0x02, 1, 1);
1042 inno_write(inno, 0x05, 0x22);
1043 inno_write(inno, 0x07, 0x22);
1047 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno)
1050 inno_write(inno, 0xb2, 0);
1052 inno_update_bits(inno, 0xb0, 0x04, 0);
1054 inno_update_bits(inno, 0xaa, 1, 1);
1057 inno_write(inno, 0x05, 0);
1058 inno_write(inno, 0x07, 0);
1061 static void inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
1067 inno_write(inno, 0x01, 0x07);
1068 inno_write(inno, 0x02, 0x91);
1074 if ((inno_read(inno, 0xc8) & 0xc0) == 0) {
1075 dev_info(inno->dev, "phy had been powered up\n");
1076 inno->phy->power_count = 1;
1079 inno_hdmi_phy_rk3328_power_off(inno);
1083 static int inno_hdmi_phy_rk3328_pre_pll_update(struct inno_hdmi_phy *inno, const struct pre_pll_config *cfg)
1088 inno_update_bits(inno, 0xa0, 1, 1);
1090 inno_update_bits(inno, 0xa0, 0x02, (cfg->vco_div_5_en & 1) << 1);
1091 inno_write(inno, 0xa1, cfg->prediv);
1097 inno_write(inno, 0xa2, val);
1098 inno_write(inno, 0xa3, cfg->fbdiv & 0xff);
1100 inno_write(inno, 0xa5, val);
1102 inno_write(inno, 0xa6, val);
1104 inno_write(inno, 0xa4, val);
1108 inno_write(inno, 0xd3, val);
1110 inno_write(inno, 0xd2, val);
1112 inno_write(inno, 0xd1, val);
1114 inno_write(inno, 0xd3, 0);
1115 inno_write(inno, 0xd2, 0);
1116 inno_write(inno, 0xd1, 0);
1120 inno_update_bits(inno, 0xa0, 1, 0);
1124 if (inno_read(inno, 0xa9) & 1) {
1130 dev_err(inno->dev, "Pre-PLL unlock\n");
1137 static unsigned long inno_hdmi_rk3328_phy_pll_recalc_rate(struct inno_hdmi_phy *inno, unsigned long parent_rate)
1144 nd = inno_read(inno, 0xa1) & 0x3f;
1145 nf = ((inno_read(inno, 0xa2) & 0x0f) << 0x08) | inno_read(inno, 0xa3);
1147 if ((inno_read(inno, 0xa2) & 0x30) == 0) {
1148 frac = inno_read(inno, 0xd3) | (inno_read(inno, 0xd2) << 0x08) | (inno_read(inno, 0xd1) << 0x10);
1151 if (inno_read(inno, 0xa0) & 0x02) {
1154 no_a = inno_read(inno, 0xa5) & 0x1f;
1155 no_b = ((inno_read(inno, 0xa5) >> 0x05) & 0x07) + 0x02;
1156 no_d = inno_read(inno, 0xa6) & 0x1f;
1165 inno->pixclock = DIV_ROUND_CLOSEST(frac, 0x3E8) * 0x3E8;
1167 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
1172 static unsigned long inno_hdmi_rk3228_phy_pll_recalc_rate(struct inno_hdmi_phy *inno, unsigned long parent_rate)
1178 nd = inno_read(inno, 0xe2) & 0x1f;
1179 nf = ((inno_read(inno, 0xe2) & 0x80) << 1) | inno_read(inno, 0xe3);
1182 if ((inno_read(inno, 0xe2) >> 0x05) & 0x1) {
1185 no_a = inno_read(inno, 0xe4) & 0x1f;
1189 no_b = ((inno_read(inno, 0xe4) >> 0x05) & 0x3) + 0x02;
1190 no_d = inno_read(inno, 0xe5) & 0x1f;
1199 inno->pixclock = vco;
1201 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
1203 return inno->pixclock;
1247 static int inno_hdmi_update_phy_table(struct inno_hdmi_phy *inno, u32 *config, struct phy_config *phy_cfg,
1278 struct inno_hdmi_phy *inno;
1286 inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
1287 if (!inno) {
1291 inno->dev = dev;
1294 inno->plat_data = (struct inno_hdmi_phy_drv_data *)match->data;
1295 if (!inno->plat_data || !inno->plat_data->ops) {
1305 inno->sysclk = devm_clk_get(inno->dev, "sysclk");
1306 if (IS_ERR(inno->sysclk)) {
1307 ret = PTR_ERR(inno->sysclk);
1308 dev_err(inno->dev, "Unable to get inno phy sysclk: %d\n", ret);
1311 ret = clk_prepare_enable(inno->sysclk);
1313 dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret);
1317 inno->regmap = devm_regmap_init_mmio(dev, regs, &inno_hdmi_phy_regmap_config);
1318 if (IS_ERR(inno->regmap)) {
1319 ret = PTR_ERR(inno->regmap);
1324 inno->phy = devm_phy_create(dev, NULL, &inno_hdmi_phy_ops);
1325 if (IS_ERR(inno->phy)) {
1327 ret = PTR_ERR(inno->phy);
1345 inno->phy_cfg = devm_kzalloc(dev, val + PHY_TAB_LEN, GFP_KERNEL);
1346 if (!inno->phy_cfg) {
1351 ret = inno_hdmi_update_phy_table(inno, phy_config, inno->phy_cfg, phy_table_size);
1361 phy_set_drvdata(inno->phy, inno);
1362 phy_set_bus_width(inno->phy, 0x08);
1371 if (inno->plat_data->ops->init) {
1372 inno->plat_data->ops->init(inno);
1375 ret = inno_hdmi_phy_clk_register(inno);
1380 inno->irq = platform_get_irq(pdev, 0);
1381 if (inno->irq > 0) {
1382 ret = devm_request_threaded_irq(inno->dev, inno->irq, inno_hdmi_phy_hardirq, inno_hdmi_phy_irq, IRQF_SHARED,
1383 dev_name(inno->dev), inno);
1388 platform_set_drvdata(pdev, inno);
1394 clk_disable_unprepare(inno->sysclk);
1400 struct inno_hdmi_phy *inno = platform_get_drvdata(pdev);
1403 clk_disable_unprepare(inno->sysclk);
1412 .name = "inno-hdmi-phy",