Lines Matching defs:gc
135 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
137 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
145 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
147 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
177 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
179 return rockchip_gpio_set_direction(gc, offset, true);
182 static int rockchip_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
184 rockchip_gpio_set(gc, offset, value);
186 return rockchip_gpio_set_direction(gc, offset, false);
189 static int rockchip_gpio_set_debounce(struct gpio_chip *gc, unsigned int offset, unsigned int debounce)
191 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
253 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, unsigned long config)
272 rockchip_gpio_set_debounce(gc, offset, debounce);
287 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
289 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
375 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
376 struct rockchip_pin_bank *bank = gc->private;
458 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
459 struct rockchip_pin_bank *bank = gc->private;
461 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
462 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
467 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
468 struct rockchip_pin_bank *bank = gc->private;
470 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
476 struct irq_chip_generic *gc;
492 gc = irq_get_domain_generic_chip(bank->domain, 0);
494 gc->reg_writel = gpio_writel_v2;
495 gc->reg_readl = gpio_readl_v2;
497 gc->reg_base = bank->reg_base;
498 gc->private = bank;
499 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
500 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
501 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
502 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
503 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
504 gc->chip_types[0].chip.irq_enable = irq_gc_mask_clr_bit;
505 gc->chip_types[0].chip.irq_disable = irq_gc_mask_set_bit;
506 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
507 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
508 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
509 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
510 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
520 gc->mask_cache = 0xffffffff;
529 struct gpio_chip *gc;
534 gc = &bank->gpio_chip;
535 gc->base = bank->pin_base;
536 gc->ngpio = bank->nr_pins;
537 gc->label = bank->name;
538 gc->parent = bank->dev;
540 gc->of_node = of_node_get(bank->of_node);
543 ret = gpiochip_add_data(gc, bank);
545 dev_err(bank->dev, "failed to add gpiochip %s, %d\n", gc->label, ret);
572 ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0, gc->base, gc->ngpio);