Lines Matching defs:bank
72 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, u32 value, unsigned int offset)
74 void __iomem *reg = bank->reg_base + offset;
76 if (bank->gpio_type == GPIO_TYPE_V2) {
83 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, unsigned int offset)
85 void __iomem *reg = bank->reg_base + offset;
88 if (bank->gpio_type == GPIO_TYPE_V2) {
97 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, u32 bit, u32 value, unsigned int offset)
99 void __iomem *reg = bank->reg_base + offset;
102 if (bank->gpio_type == GPIO_TYPE_V2) {
119 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, u32 bit, unsigned int offset)
121 void __iomem *reg = bank->reg_base + offset;
124 if (bank->gpio_type == GPIO_TYPE_V2) {
137 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
140 raw_spin_lock_irqsave(&bank->slock, flags);
141 rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
142 raw_spin_unlock_irqrestore(&bank->slock, flags);
147 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
150 data = readl(bank->reg_base + bank->gpio_regs->ext_port);
159 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
162 data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
169 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
172 rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
191 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
192 const struct rockchip_gpio_regs *reg = bank->gpio_regs;
198 if (!IS_ERR(bank->db_clk)) {
200 freq = clk_get_rate(bank->db_clk);
212 raw_spin_lock_irqsave(&bank->slock, flags);
218 cur_div_reg = readl(bank->reg_base + reg->dbclk_div_con);
220 writel(div_reg, bank->reg_base + reg->dbclk_div_con);
222 rockchip_gpio_writel_bit(bank, offset, 1, reg->dbclk_div_en);
225 rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
228 rockchip_gpio_writel_bit(bank, offset, 0, reg->dbclk_div_en);
231 rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
234 raw_spin_unlock_irqrestore(&bank->slock, flags);
239 clk_prepare_enable(bank->db_clk);
241 clk_disable_unprepare(bank->db_clk);
289 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
292 if (!bank->domain) {
296 virq = irq_create_mapping(bank->domain, offset);
317 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
318 const struct rockchip_gpio_regs *reg = bank->gpio_regs;
321 dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
325 pend = readl_relaxed(bank->reg_base + reg->int_status);
332 virq = irq_find_mapping(bank->domain, irq);
334 dev_err(bank->dev, "unmapped irq %d\n", irq);
338 dev_dbg(bank->dev, "handling irq %d\n", irq);
344 if (bank->toggle_edge_mode & BIT(irq)) {
348 data = readl_relaxed(bank->reg_base + reg->ext_port);
350 raw_spin_lock_irqsave(&bank->slock, flags);
352 polarity = readl_relaxed(bank->reg_base + reg->int_polarity);
358 writel(polarity, bank->reg_base + reg->int_polarity);
360 raw_spin_unlock_irqrestore(&bank->slock, flags);
363 data = readl_relaxed(bank->reg_base + reg->ext_port);
376 struct rockchip_pin_bank *bank = gc->private;
384 raw_spin_lock_irqsave(&bank->slock, flags);
386 rockchip_gpio_writel_bit(bank, d->hwirq, 0, bank->gpio_regs->port_ddr);
388 raw_spin_unlock_irqrestore(&bank->slock, flags);
396 raw_spin_lock_irqsave(&bank->slock, flags);
398 level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
399 polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
403 if (bank->gpio_type == GPIO_TYPE_V2) {
404 bank->toggle_edge_mode &= ~mask;
405 rockchip_gpio_writel_bit(bank, d->hwirq, 1, bank->gpio_regs->int_bothedge);
408 bank->toggle_edge_mode |= mask;
415 data = readl(bank->reg_base + bank->gpio_regs->ext_port);
424 bank->toggle_edge_mode &= ~mask;
429 bank->toggle_edge_mode &= ~mask;
434 bank->toggle_edge_mode &= ~mask;
439 bank->toggle_edge_mode &= ~mask;
448 rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
449 rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
451 raw_spin_unlock_irqrestore(&bank->slock, flags);
459 struct rockchip_pin_bank *bank = gc->private;
461 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
462 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
468 struct rockchip_pin_bank *bank = gc->private;
470 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
473 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
479 bank->domain = irq_domain_add_linear(bank->of_node, 0x20, &irq_generic_chip_ops, NULL);
480 if (!bank->domain) {
481 dev_warn(bank->dev, "could not initialize irq domain for bank %s\n", bank->name);
485 ret = irq_alloc_domain_generic_chips(bank->domain, 0x20, 1, bank->name, handle_level_irq, clr, 0, 0);
487 dev_err(bank->dev, "could not alloc generic chips for bank %s\n", bank->name);
488 irq_domain_remove(bank->domain);
492 gc = irq_get_domain_generic_chip(bank->domain, 0);
493 if (bank->gpio_type == GPIO_TYPE_V2) {
497 gc->reg_base = bank->reg_base;
498 gc->private = bank;
499 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
500 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
510 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
517 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
518 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);
519 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
522 irq_set_chained_handler_and_data(bank->irq, rockchip_irq_demux, bank);
527 static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
532 bank->gpio_chip = rockchip_gpiolib_chip;
534 gc = &bank->gpio_chip;
535 gc->base = bank->pin_base;
536 gc->ngpio = bank->nr_pins;
537 gc->label = bank->name;
538 gc->parent = bank->dev;
540 gc->of_node = of_node_get(bank->of_node);
543 ret = gpiochip_add_data(gc, bank);
545 dev_err(bank->dev, "failed to add gpiochip %s, %d\n", gc->label, ret);
559 if (!of_property_read_bool(bank->of_node, "gpio-ranges")) {
560 struct device_node *pctlnp = of_get_parent(bank->of_node);
574 dev_err(bank->dev, "Failed to add pin range\n");
579 ret = rockchip_interrupts_register(bank);
581 dev_err(bank->dev, "failed to register interrupt, %d\n", ret);
588 gpiochip_remove(&bank->gpio_chip);
593 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
598 if (of_address_to_resource(bank->of_node, 0, &res)) {
602 bank->reg_base = devm_ioremap_resource(bank->dev, &res);
603 if (IS_ERR(bank->reg_base)) {
604 return PTR_ERR(bank->reg_base);
607 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
608 if (!bank->irq) {
612 bank->clk = of_clk_get(bank->of_node, 0);
613 if (IS_ERR(bank->clk)) {
614 return PTR_ERR(bank->clk);
617 clk_prepare_enable(bank->clk);
618 id = readl(bank->reg_base + gpio_regs_v2.version_id);
621 bank->gpio_regs = &gpio_regs_v2;
622 bank->gpio_type = GPIO_TYPE_V2;
623 bank->db_clk = of_clk_get(bank->of_node, 1);
624 if (IS_ERR(bank->db_clk)) {
625 dev_err(bank->dev, "cannot find debounce clk\n");
626 bank->db_clk = NULL;
630 bank->gpio_regs = &gpio_regs_v1;
631 bank->gpio_type = GPIO_TYPE_V1;
640 struct rockchip_pin_bank *bank;
644 bank = info->ctrl->pin_banks;
645 for (i = 0; i < info->ctrl->nr_banks; i++, bank++) {
646 if (bank->bank_num == id) {
652 return found ? bank : NULL;
661 struct rockchip_pin_bank *bank = NULL;
679 bank = rockchip_gpio_find_bank(pctldev, id);
680 if (!bank) {
684 bank->dev = dev;
685 bank->of_node = dev->of_node;
687 raw_spin_lock_init(&bank->slock);
689 ret = rockchip_get_bank_data(bank);
694 ret = rockchip_gpiolib_register(bank);
699 platform_set_drvdata(pdev, bank);
700 dev_info(dev, "probed %s (%s)\n", bank->name, dev_name(dev));
704 clk_disable_unprepare(bank->clk);
711 struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
713 clk_disable_unprepare(bank->clk);
714 gpiochip_remove(&bank->gpio_chip);
721 .compatible = "rockchip,gpio-bank",