Lines Matching refs:gpll
27 gpll,
125 PNAME(mux_gpll_cpll_p) = {"gpll", "cpll"};
126 PNAME(mux_gpll_cpll_apll_p) = {"gpll", "cpll", "apll"};
129 PNAME(mux_cpll_gpll_npll_p) = {"cpll", "gpll", "npll"};
130 PNAME(mux_gpll_cpll_npll_p) = {"gpll", "cpll", "npll"};
133 PNAME(mux_24m_npll_gpll_usb480m_p) = {"xin24m", "npll", "gpll", "usb480m"};
136 PNAME(mux_gpll_cpll_npll_24m_p) = {"gpll", "cpll", "npll", "xin24m"};
145 PNAME(mux_gpll_usb480m_cpll_npll_p) = {"gpll", "usb480m", "cpll", "npll"};
153 PNAME(mux_gpll_xin24m_p) = {"gpll", "xin24m"};
154 PNAME(mux_gpll_cpll_xin24m_p) = {"gpll", "cpll", "xin24m"};
155 PNAME(mux_gpll_xin24m_cpll_npll_p) = {"gpll", "xin24m", "cpll", "npll"};
167 PNAME(mux_gpll_usb480m_cpll_ppll_p) = {"gpll", "usb480m", "cpll", "ppll"};
182 [gpll] =
183 PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK1808_PLL_CON(24), RK1808_MODE_CON, 6, 3, 0, rk1808_pll_rates),
255 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(0), 0, GFLAGS),
265 COMPOSITE_NOMUX(MSCLK_CORE_NIU, "msclk_core_niu", "gpll", CLK_IS_CRITICAL, RK1808_CLKSEL_CON(18), 0, 5, DFLAGS,
341 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(8), 6, GFLAGS),
347 COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IS_CRITICAL, RK1808_CLKSEL_CON(3), 8, 5, DFLAGS,
392 COMPOSITE_NOMUX(SCLK_TXESC, "clk_txesc", "gpll", 0, RK1808_CLKSEL_CON(9), 0, 12, DFLAGS, RK1808_CLKGATE_CON(3), 7,