Lines Matching refs:MUX
195 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(39), 14, 2, MFLAGS);
198 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(42), 14, 2, MFLAGS);
201 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(45), 14, 2, MFLAGS);
204 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(48), 14, 2, MFLAGS);
207 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(51), 14, 2, MFLAGS);
210 MUX(0, "clk_uart6_mux", mux_uart6_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(54), 14, 2, MFLAGS);
213 MUX(0, "clk_uart7_mux", mux_uart7_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(57), 14, 2, MFLAGS);
216 MUX(0, "dclk_vopraw_mux", mux_dclk_vopraw_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(5), 14, 2, MFLAGS);
219 MUX(0, "dclk_voplite_mux", mux_dclk_voplite_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(7), 14, 2, MFLAGS);
222 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(30), 15, 1, MFLAGS);
225 MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(32), 10,
229 MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(34), 10,
233 MUX(0, "clk_i2s1_2ch_mux", mux_i2s1_2ch_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(36), 10, 2, MFLAGS);
235 static struct rockchip_clk_branch rk1808_rtc32k_pmu_fracmux __initdata = MUX(
239 MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT, RK1808_PMU_CLKSEL_CON(4), 14, 2, MFLAGS);
246 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, RK1808_MODE_CON, 10, 2, MFLAGS),
296 MUX(0, "clk_npu_pre", mux_npu_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(1), 15, 1, MFLAGS),
517 MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK1808_CLKSEL_CON(27), 0, 1,
527 MUX(SCLK_GMAC_RGMII_SPEED, "clk_gmac_rgmii_speed", mux_gmac_rgmii_speed_p, CLK_SET_RATE_PARENT,
529 MUX(SCLK_GMAC_RMII_SPEED, "clk_gmac_rmii_speed", mux_gmac_rmii_speed_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(27),
531 MUX(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", mux_gmac_rx_tx_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(27), 4, 1, MFLAGS),