Lines Matching refs:parent
645 struct node *parent = node->parent;
650 for_each_label(parent->labels, label) return;
652 for_each_property(parent, prop) return;
654 for_each_child(parent, child) return;
656 delete_node(parent);
776 if (!node->parent) {
785 addr_cells = node_addr_cells(node->parent);
786 size_cells = node_size_cells(node->parent);
809 if (!node->parent) {
814 p_addr_cells = node_addr_cells(node->parent);
815 p_size_cells = node_size_cells(node->parent);
825 ranges, c_addr_cells, node->parent->fullpath, p_addr_cells);
831 ranges, c_size_cells, node->parent->fullpath, p_size_cells);
836 "(parent #address-cells == %d, child #address-cells == %d, "
901 if (!node->parent || (node->parent->bus != &pci_bus)) {
913 prop = get_property(node->parent, "bus-range");
935 if (!node->parent || (node->parent->bus != &pci_bus)) {
1015 if (!node->parent || (node->parent->bus != &simple_bus)) {
1031 if (node->parent->parent && !(node->bus == &simple_bus)) {
1037 size = node_addr_cells(node->parent);
1096 if (!node->parent || (node->parent->bus != &i2c_bus)) {
1196 if (!node->parent || (node->parent->bus != &spi_bus)) {
1200 if (get_property(node->parent, "spi-slave")) {
1226 if (node->parent && node->parent->bus) {
1253 if (!node->parent) {
1263 if (node->parent->addr_cells == -1) {
1267 if (node->parent->size_cells == -1) {
1279 if (!node->parent || node->addr_cells < 0 || node->size_cells < 0) {
1401 if (node->parent != dti->dt) {
1546 WARNING_PROPERTY_PHANDLE_CELLS(msi_parent, "msi-parent", "#msi-cells", true);
1667 struct node *irq_node = NULL, *parent = node;
1681 while (parent && !prop) {
1682 if (parent != node && node_is_interrupt_provider(parent)) {
1683 irq_node = parent;
1687 prop = get_property(parent, "interrupt-parent");
1696 FAIL_PROP(c, dti, parent, prop, "Invalid phandle");
1702 FAIL_PROP(c, dti, parent, prop, "Bad phandle");
1712 parent = parent->parent;
1716 FAIL(c, dti, node, "Missing interrupt-parent");
1754 /* The parent of 'port' nodes can be either 'ports' or a device */
1755 if (!node->parent->bus && (streq(node->parent->name, "ports") || get_property(node, "reg"))) {
1756 node->parent->bus = &graph_ports_bus;
1813 if (node->parent->addr_cells != 1) {
1815 node->parent->addr_cells);
1817 if (node->parent->size_cells != 0) {
1819 node->parent->size_cells);
1866 if (!node->parent || node->parent->bus != &graph_port_bus) {