Lines Matching refs:parent
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
49 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
51 * @best_parent_hw: The most appropriate parent clock that fulfills the
120 * parent rate is an input parameter. It is up to the caller to
126 * supported by the clock. The parent rate is an input/output
130 * actually supported by the clock, and optionally the parent clock
134 * possible parents specify a new parent by passing in the index
135 * as a u8 corresponding to the parent in either the .parent_names
140 * @get_parent: Queries the hardware to determine the parent of a clock. The
142 * the parent clock. This index can be applied to either the
144 * translates the parent value read from hardware into an array
152 * of .round_rate call. The third argument gives the parent rate
156 * @set_rate_and_parent: Change the rate and the parent of this clock. The
159 * third argument gives the parent rate which is likely helpful
161 * argument gives the parent index. This callback is optional (and
163 * for clocks that can tolerate switching the rate and the parent
168 * is expressed in ppb (parts per billion). The parent accuracy is
171 * set then clock accuracy will be initialized to parent accuracy
172 * or 0 (perfect clock) if clock has no parent.
249 * struct clk_parent_data - clk parent information
250 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
251 * @fw_name: parent name local to provider registering clk
252 * @name: globally unique parent name (used as a fallback)
253 * @index: parent index local to provider registering clk (if @fw_name absent)
269 * @parent_data: array of parent data for all possible parents (when some
326 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
351 * @parent_name: name of clock's parent
362 * @parent_hw: pointer to parent clk
373 * @parent_data: parent clk data
384 * @parent_name: name of clock's parent
397 * @parent_hw: pointer to parent clk
410 * @parent_name: name of clock's parent
473 * @parent_name: name of this clock's parent
488 * @parent_hw: pointer to parent clk
503 * @parent_data: parent clk data
590 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate,
592 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate,
609 * @parent_name: name of clock's parent
624 * @parent_name: name of clock's parent
640 * @parent_hw: pointer to parent clk
656 * @parent_data: parent clk data
672 * @parent_name: name of clock's parent
690 * @parent_hw: pointer to parent clk
708 * @parent_data: parent clk data
730 * @table: array of register values corresponding to the parent index
748 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
818 * parent clock rate divided by div and multiplied by mult.
910 * leaving the parent rate unmodified.
941 * @brother_hw: a member of clk_composite who has the common parent clocks