Lines Matching defs:table

529  * @table:    array of value/divider pairs, last entry should have div = 0

569     const struct clk_div_table *table;

589                                   const struct clk_div_table *table, unsigned long flags, unsigned long width);

591                                const struct clk_div_table *table, u8 width, unsigned long flags);

593                                   const struct clk_div_table *table, u8 width, unsigned long flags, unsigned int val);

594 int divider_get_val(unsigned long rate, unsigned long parent_rate, const struct clk_div_table *table, u8 width,

601                                          const struct clk_div_table *table, spinlock_t *lock);

604                                        const struct clk_div_table *table, spinlock_t *lock);

668  * clk_hw_register_divider_table - register a table based divider clock with

678  * @table: array of divider/value pairs ending with a div set to 0

681 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, shift, width, clk_divider_flags, table,      \

684                               (clk_divider_flags), (table), (lock))

686  * clk_hw_register_divider_table_parent_hw - register a table based divider

696  * @table: array of divider/value pairs ending with a div set to 0

700                                                 table, lock)                                                           \

702                               (clk_divider_flags), (table), (lock))

704  * clk_hw_register_divider_table_parent_data - register a table based divider

714  * @table: array of divider/value pairs ending with a div set to 0

718                                                   table, lock)                                                         \

720                               (clk_divider_flags), (table), (lock))

730  * @table:    array of register values corresponding to the parent index

757     u32 *table;

779                                      u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock);

782                                    u8 clk_mux_flags, u32 *table, spinlock_t *lock);

787 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, flags, reg, shift, mask, clk_mux_flags, table, \

790                           (mask), (clk_mux_flags), (table), (lock))

802 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, unsigned int val);

803 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);

1039                                       const struct clk_div_table *table, u8 width, unsigned long flags)

1041     return divider_round_rate_parent(hw, clk_hw_get_parent(hw), rate, prate, table, width, flags);

1045                                          const struct clk_div_table *table, u8 width, unsigned long flags,

1048     return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), rate, prate, table, width, flags, val);