Lines Matching defs:rate
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
45 * @rate: Requested clock rate. This field will be adjusted by
47 * @min_rate: Minimum rate imposed by clk users.
48 * @max_rate: Maximum rate imposed by clk users.
49 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
56 unsigned long rate;
119 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
120 * parent rate is an input parameter. It is up to the caller to
122 * Returns the calculated rate. Optional, but recommended - if
123 * this op is not set then clock rate will be initialized to 0.
125 * @round_rate: Given a target rate as input, returns the closest rate actually
126 * supported by the clock. The parent rate is an input/output
129 * @determine_rate: Given a target rate as input, returns the closest rate
131 * that should be used to provide the clock rate.
150 * @set_rate: Change the rate of this clock. The requested rate is specified
152 * of .round_rate call. The third argument gives the parent rate
156 * @set_rate_and_parent: Change the rate and the parent of this clock. The
157 * requested rate is specified by the second argument, which
159 * third argument gives the parent rate which is likely helpful
163 * for clocks that can tolerate switching the rate and the parent
197 * such as rate or parents.
232 long (*round_rate)(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate);
236 int (*set_rate)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate);
237 int (*set_rate_and_parent)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index);
319 * struct clk_fixed_rate - fixed-rate clock
347 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
353 * @fixed_rate: non-adjustable clock rate
358 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
364 * @fixed_rate: non-adjustable clock rate
369 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
375 * @fixed_rate: non-adjustable clock rate
380 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
386 * @fixed_rate: non-adjustable clock rate
393 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
399 * @fixed_rate: non-adjustable clock rate
406 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
412 * @fixed_rate: non-adjustable clock rate
590 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate,
592 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate,
594 int divider_get_val(unsigned long rate, unsigned long parent_rate, const struct clk_div_table *table, u8 width,
748 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
818 * parent clock rate divided by div and multiplied by mult.
873 void (*approximation)(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate, unsigned long *m,
908 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
910 * leaving the parent rate unmodified.
939 * @rate_hw: handle between composite and hardware-specific rate clock
945 * @rate_ops: clock ops for rate
1038 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate,
1041 return divider_round_rate_parent(hw, clk_hw_get_parent(hw), rate, prate, table, width, flags);
1044 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate,
1048 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), rate, prate, table, width, flags, val);
1054 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);