Lines Matching refs:ctlr
252 struct spi_controller *ctlr = spi->controller;
253 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
284 static void rockchip_spi_handle_err(struct spi_controller *ctlr, struct spi_message *msg)
286 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
298 dmaengine_terminate_async(ctlr->dma_tx);
302 dmaengine_terminate_async(ctlr->dma_rx);
363 struct spi_controller *ctlr = dev_id;
364 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
368 ctlr->slave_abort(ctlr);
384 spi_finalize_current_transfer(ctlr);
390 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs, struct spi_controller *ctlr, struct spi_transfer *xfer)
414 struct spi_controller *ctlr = data;
415 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
424 spi_finalize_current_transfer(ctlr);
429 struct spi_controller *ctlr = data;
430 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
436 wait_for_tx_idle(rs, ctlr->slave);
438 spi_finalize_current_transfer(ctlr);
455 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs, struct spi_controller *ctlr, struct spi_transfer *xfer)
473 dmaengine_slave_config(ctlr->dma_rx, &rxconf);
475 rxdesc = dmaengine_prep_slave_sg(ctlr->dma_rx, xfer->rx_sg.sgl, xfer->rx_sg.nents, DMA_DEV_TO_MEM,
482 rxdesc->callback_param = ctlr;
494 dmaengine_slave_config(ctlr->dma_tx, &txconf);
496 txdesc = dmaengine_prep_slave_sg(ctlr->dma_tx, xfer->tx_sg.sgl, xfer->tx_sg.nents, DMA_MEM_TO_DEV,
500 dmaengine_terminate_sync(ctlr->dma_rx);
506 txdesc->callback_param = ctlr;
512 ctlr->dma_rx->cookie = dmaengine_submit(rxdesc);
513 dma_async_issue_pending(ctlr->dma_rx);
525 dma_async_issue_pending(ctlr->dma_tx);
577 * ctlr->bits_per_word_mask, so this shouldn't
637 static int rockchip_spi_slave_abort(struct spi_controller *ctlr)
639 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
645 dmaengine_terminate_sync(ctlr->dma_rx);
647 dmaengine_terminate_sync(ctlr->dma_tx);
651 dmaengine_pause(ctlr->dma_rx);
652 status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state);
653 dmaengine_terminate_sync(ctlr->dma_rx);
689 complete(&ctlr->xfer_completion);
694 static int rockchip_spi_transfer_one(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *xfer)
696 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
714 use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
716 ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
722 return rockchip_spi_prepare_dma(rs, ctlr, xfer);
725 return rockchip_spi_prepare_irq(rs, ctlr, xfer);
728 static bool rockchip_spi_can_dma(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *xfer)
730 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
744 struct spi_controller *ctlr;
752 ctlr = spi_alloc_slave(&pdev->dev, sizeof(struct rockchip_spi));
754 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
756 if (!ctlr) {
760 platform_set_drvdata(pdev, ctlr);
762 rs = spi_controller_get_devdata(ctlr);
763 ctlr->slave = slave_mode;
806 ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL, IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
837 ctlr->auto_runtime_pm = true;
838 ctlr->bus_num = pdev->id;
839 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
841 ctlr->mode_bits |= SPI_NO_CS;
842 ctlr->slave_abort = rockchip_spi_slave_abort;
844 ctlr->flags = SPI_MASTER_GPIO_SS;
845 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
852 ctlr->num_chipselect = num_cs;
853 ctlr->use_gpio_descriptors = true;
855 ctlr->dev.of_node = pdev->dev.of_node;
856 ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
857 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
858 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
860 ctlr->set_cs = rockchip_spi_set_cs;
861 ctlr->transfer_one = rockchip_spi_transfer_one;
862 ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
863 ctlr->handle_err = rockchip_spi_handle_err;
865 ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
866 if (IS_ERR(ctlr->dma_tx)) {
868 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
873 ctlr->dma_tx = NULL;
876 ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
877 if (IS_ERR(ctlr->dma_rx)) {
878 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
883 ctlr->dma_rx = NULL;
886 if (ctlr->dma_tx && ctlr->dma_rx) {
889 ctlr->can_dma = rockchip_spi_can_dma;
894 ctlr->mode_bits |= SPI_CS_HIGH;
895 if (ctlr->can_dma && slave_mode) {
915 ret = devm_spi_register_controller(&pdev->dev, ctlr);
924 if (ctlr->dma_rx) {
925 dma_release_channel(ctlr->dma_rx);
928 if (ctlr->dma_tx) {
929 dma_release_channel(ctlr->dma_tx);
938 spi_controller_put(ctlr);
945 struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
946 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
957 if (ctlr->dma_tx) {
958 dma_release_channel(ctlr->dma_tx);
960 if (ctlr->dma_rx) {
961 dma_release_channel(ctlr->dma_rx);
964 spi_controller_put(ctlr);
973 struct spi_controller *ctlr = dev_get_drvdata(dev);
975 ret = spi_controller_suspend(ctlr);
993 struct spi_controller *ctlr = dev_get_drvdata(dev);
994 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1003 ret = spi_controller_resume(ctlr);
1016 struct spi_controller *ctlr = dev_get_drvdata(dev);
1017 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1028 struct spi_controller *ctlr = dev_get_drvdata(dev);
1029 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);