Lines Matching defs:rs
210 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
212 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
215 static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
221 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY) &&
222 !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))) {
226 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) {
232 dev_warn(rs->dev, "spi controller is in busy state!\n");
235 static u32 get_fifo_len(struct rockchip_spi *rs)
239 ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
253 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
257 if (cs_asserted == rs->cs_asserted[spi->chip_select]) {
263 pm_runtime_get_sync(rs->dev);
266 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
268 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
272 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
274 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
278 pm_runtime_put(rs->dev);
281 rs->cs_asserted[spi->chip_select] = cs_asserted;
286 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
292 spi_enable_chip(rs, false);
295 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
297 if (atomic_read(&rs->state) & TXDMA) {
301 if (atomic_read(&rs->state) & RXDMA) {
306 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
308 u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
309 u32 words = min(rs->tx_left, tx_free);
311 rs->tx_left -= words;
315 if (rs->n_bytes == 1) {
316 txw = *(u8 *)rs->tx;
318 txw = *(u16 *)rs->tx;
321 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
322 rs->tx += rs->n_bytes;
326 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
328 u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
329 u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
337 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
340 words = rs->rx_left - rx_left;
344 rs->rx_left = rx_left;
346 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
348 if (!rs->rx) {
352 if (rs->n_bytes == 1) {
353 *(u8 *)rs->rx = (u8)rxw;
355 *(u16 *)rs->rx = (u16)rxw;
357 rs->rx += rs->n_bytes;
364 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
367 if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) {
369 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
370 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
375 if (rs->tx_left) {
376 rockchip_spi_pio_writer(rs);
379 rockchip_spi_pio_reader(rs);
380 if (!rs->rx_left) {
381 spi_enable_chip(rs, false);
382 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
383 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
390 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs, struct spi_controller *ctlr, struct spi_transfer *xfer)
392 rs->tx = xfer->tx_buf;
393 rs->rx = xfer->rx_buf;
394 rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
395 rs->rx_left = xfer->len / rs->n_bytes;
397 if (rs->cs_inactive) {
398 writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
400 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
402 spi_enable_chip(rs, true);
404 if (rs->tx_left) {
405 rockchip_spi_pio_writer(rs);
415 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
416 int state = atomic_fetch_andnot(RXDMA, &rs->state);
417 if (state & TXDMA && !rs->slave_abort) {
420 if (rs->cs_inactive) {
421 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
423 spi_enable_chip(rs, false);
430 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
431 int state = atomic_fetch_andnot(TXDMA, &rs->state);
432 if (state & RXDMA && !rs->slave_abort) {
436 wait_for_tx_idle(rs, ctlr->slave);
437 spi_enable_chip(rs, false);
455 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs, struct spi_controller *ctlr, struct spi_transfer *xfer)
459 atomic_set(&rs->state, 0);
461 rs->tx = xfer->tx_buf;
462 rs->rx = xfer->rx_buf;
468 .src_addr = rs->dma_addr_rx,
469 .src_addr_width = rs->n_bytes,
470 .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes),
489 .dst_addr = rs->dma_addr_tx,
490 .dst_addr_width = rs->n_bytes,
491 .dst_maxburst = rs->fifo_len / 4,
511 atomic_or(RXDMA, &rs->state);
516 if (rs->cs_inactive) {
517 writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
520 spi_enable_chip(rs, true);
523 atomic_or(TXDMA, &rs->state);
532 static int rockchip_spi_config(struct rockchip_spi *rs, struct spi_device *spi, struct spi_transfer *xfer, bool use_dma,
543 rs->slave_abort = false;
545 cr0 |= rs->rsd << CR0_RSD_OFFSET;
580 dev_err(rs->dev, "unknown bits per word: %d\n", xfer->bits_per_word);
597 if (rs->high_speed_state) {
598 if (rs->freq > IO_DRIVER_4MA_MAX_SCLK_OUT) {
599 pinctrl_select_state(rs->dev->pins->p, rs->high_speed_state);
601 pinctrl_select_state(rs->dev->pins->p, rs->dev->pins->default_state);
605 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
606 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
612 if ((xfer->len / rs->n_bytes) < rs->fifo_len) {
613 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
615 writel_relaxed(rs->fifo_len / ROCKCHIP_XFER_LEN_DIV - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
618 writel_relaxed(rs->fifo_len / ROCKCHIP_XFER_LEN_DIV - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
619 writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1, rs->regs + ROCKCHIP_SPI_DMARDLR);
620 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
626 writel_relaxed(ROCKCHIP_SPI_BAUDRATE_MUL * DIV_ROUND_UP(rs->freq, ROCKCHIP_SPI_BAUDRATE_MUL * xfer->speed_hz),
627 rs->regs + ROCKCHIP_SPI_BAUDR);
639 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
644 if (atomic_read(&rs->state) & RXDMA)
646 if (atomic_read(&rs->state) & TXDMA)
650 if (atomic_read(&rs->state) & RXDMA) {
654 atomic_set(&rs->state, 0);
656 rs->rx = rs->xfer->rx_buf;
657 rs->xfer->len = 0;
658 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
660 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
664 rs->rx += rs->xfer->len - rs->n_bytes * state.residue;
668 /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */
669 if (rs->rx) {
670 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
672 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
674 if (rs->n_bytes == 1) {
675 *(u8 *)rs->rx = (u8)rxw;
677 *(u16 *)rs->rx = (u16)rxw;
679 rs->rx += rs->n_bytes;
682 rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf);
686 atomic_set(&rs->state, 0);
687 spi_enable_chip(rs, false);
688 rs->slave_abort = true;
696 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
700 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
703 dev_err(rs->dev, "No buffer for transfer\n");
708 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
712 rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
713 rs->xfer = xfer;
716 ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
722 return rockchip_spi_prepare_dma(rs, ctlr, xfer);
725 return rockchip_spi_prepare_irq(rs, ctlr, xfer);
730 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
737 return xfer->len / bytes_per_word >= rs->fifo_len;
743 struct rockchip_spi *rs;
762 rs = spi_controller_get_devdata(ctlr);
767 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
768 if (IS_ERR(rs->regs)) {
769 ret = PTR_ERR(rs->regs);
773 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
774 if (IS_ERR(rs->apb_pclk)) {
776 ret = PTR_ERR(rs->apb_pclk);
780 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
781 if (IS_ERR(rs->spiclk)) {
783 ret = PTR_ERR(rs->spiclk);
787 ret = clk_prepare_enable(rs->apb_pclk);
793 ret = clk_prepare_enable(rs->spiclk);
799 spi_enable_chip(rs, false);
811 rs->dev = &pdev->dev;
812 rs->freq = clk_get_rate(rs->spiclk);
816 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8), 1000000000 >> 8);
818 dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n", rs->freq, rsd_nsecs);
821 dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n", rs->freq, rsd_nsecs,
822 CR0_RSD_MAX * 1000000000U / rs->freq);
824 rs->rsd = rsd;
827 rs->fifo_len = get_fifo_len(rs);
828 if (!rs->fifo_len) {
857 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
858 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
865 ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
872 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
876 ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
882 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
887 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
888 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
892 switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
896 rs->cs_inactive = true;
898 rs->cs_inactive = false;
902 rs->cs_inactive = false;
908 rs->high_speed_state = pinctrl_lookup_state(pinctrl, "high_speed");
909 if (IS_ERR_OR_NULL(rs->high_speed_state)) {
911 rs->high_speed_state = NULL;
934 clk_disable_unprepare(rs->spiclk);
936 clk_disable_unprepare(rs->apb_pclk);
946 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
950 clk_disable_unprepare(rs->spiclk);
951 clk_disable_unprepare(rs->apb_pclk);
994 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1005 clk_disable_unprepare(rs->spiclk);
1006 clk_disable_unprepare(rs->apb_pclk);
1017 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1019 clk_disable_unprepare(rs->spiclk);
1020 clk_disable_unprepare(rs->apb_pclk);
1029 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1031 ret = clk_prepare_enable(rs->apb_pclk);
1036 ret = clk_prepare_enable(rs->spiclk);
1038 clk_disable_unprepare(rs->apb_pclk);