Lines Matching defs:period
55 unsigned long period;
88 tmp = readl_relaxed(pc->base + pc->data->regs.period);
90 state->period = DIV_ROUND_CLOSEST_ULL(tmp, pc->clk_rate);
111 unsigned long period, duty;
117 * Since period and duty cycle registers have a width of 32
118 * bits, every possible input period can be obtained using the
121 div = (u64)pc->clk_rate * state->period;
122 period = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
129 * Lock the period and duty of previous configuration, then
130 * change the duty and period, that would not be effective.
159 writel(period, pc->base + pc->data->regs.period);
173 * the configuration of duty, period and polarity
174 * would be effective together at next period.
278 .period = 0x08,
294 .period = 0x04,
310 .period = 0x04,
326 .period = 0x04,