Lines Matching defs:pc

77     struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);

78     u32 enable_conf = pc->data->enable_conf;

83     ret = clk_enable(pc->pclk);

88     tmp = readl_relaxed(pc->base + pc->data->regs.period);

89     tmp *= pc->data->prescaler * NSEC_PER_SEC;

90     state->period = DIV_ROUND_CLOSEST_ULL(tmp, pc->clk_rate);

92     tmp = readl_relaxed(pc->base + pc->data->regs.duty);

93     tmp *= pc->data->prescaler * NSEC_PER_SEC;

94     state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, pc->clk_rate);

96     val = readl_relaxed(pc->base + pc->data->regs.ctrl);

99     if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE)) {

105     clk_disable(pc->pclk);

110     struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);

121     div = (u64)pc->clk_rate * state->period;

122     period = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);

124     div = (u64)pc->clk_rate * state->duty_cycle;

125     duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);

132     ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);

133     if (pc->data->vop_pwm) {

134         if (pc->vop_pwm_en) {

143         pc->oneshot = false;

146         pc->oneshot = true;

149         pc->oneshot = false;

154     if (pc->data->supports_lock) {

156         writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);

159     writel(period, pc->base + pc->data->regs.period);

160     writel(duty, pc->base + pc->data->regs.duty);

162     if (pc->data->supports_polarity) {

176     if (pc->data->supports_lock) {

180     writel(ctrl, pc->base + pc->data->regs.ctrl);

186     struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);

187     u32 enable_conf = pc->data->enable_conf;

192         ret = clk_enable(pc->clk);

198     val = readl_relaxed(pc->base + pc->data->regs.ctrl);

199     val &= ~pc->data->enable_conf_mask;

201     if (PWM_OUTPUT_CENTER & pc->data->enable_conf_mask) {

202         if (pc->center_aligned) {

209         if (pc->oneshot) {

216     writel_relaxed(val, pc->base + pc->data->regs.ctrl);

217     if (pc->data->vop_pwm) {

218         pc->vop_pwm_en = enable;

222         clk_disable(pc->clk);

230     struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);

235     ret = clk_enable(pc->pclk);

243     if (state->polarity != curstate.polarity && enabled && !pc->data->supports_lock) {

260         ret = pinctrl_select_state(pc->pinctrl, pc->active_state);

263     clk_disable(pc->pclk);

348     struct rockchip_pwm_chip *pc;

359     pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);

360     if (!pc) {

365     pc->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));

366     if (IS_ERR(pc->base)) {

367         return PTR_ERR(pc->base);

370     pc->clk = devm_clk_get(&pdev->dev, "pwm");

371     if (IS_ERR(pc->clk)) {

372         pc->clk = devm_clk_get(&pdev->dev, NULL);

373         if (IS_ERR(pc->clk)) {

374             return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk), "Can't get bus clk\n");

380         pc->pclk = devm_clk_get(&pdev->dev, "pclk");

382         pc->pclk = pc->clk;

385     if (IS_ERR(pc->pclk)) {

386         ret = PTR_ERR(pc->pclk);

393     ret = clk_prepare_enable(pc->clk);

399     ret = clk_prepare_enable(pc->pclk);

405     pc->pinctrl = devm_pinctrl_get(&pdev->dev);

406     if (IS_ERR(pc->pinctrl)) {

408         return PTR_ERR(pc->pinctrl);

411     pc->active_state = pinctrl_lookup_state(pc->pinctrl, "active");

412     if (IS_ERR(pc->active_state)) {

414         return PTR_ERR(pc->active_state);

417     platform_set_drvdata(pdev, pc);

419     pc->data = id->data;

420     pc->chip.dev = &pdev->dev;

421     pc->chip.ops = &rockchip_pwm_ops;

422     pc->chip.base = -1;

423     pc->chip.npwm = 1;

424     pc->clk_rate = clk_get_rate(pc->clk);

426     if (pc->data->supports_polarity) {

427         pc->chip.of_xlate = of_pwm_xlate_with_flags;

428         pc->chip.of_pwm_n_cells = PWM_CELLS;

431     enable_conf = pc->data->enable_conf;

432     ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);

435     pc->center_aligned = device_property_read_bool(&pdev->dev, "center-aligned");

437     ret = pwmchip_add(&pc->chip);

445         clk_disable(pc->clk);

448     clk_disable(pc->pclk);

453     clk_disable_unprepare(pc->pclk);

455     clk_disable_unprepare(pc->clk);

462     struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);

464     clk_unprepare(pc->pclk);

465     clk_unprepare(pc->clk);

467     return pwmchip_remove(&pc->chip);