Lines Matching defs:data
45 const struct rockchip_pwm_data *data;
78 u32 enable_conf = pc->data->enable_conf;
88 tmp = readl_relaxed(pc->base + pc->data->regs.period);
89 tmp *= pc->data->prescaler * NSEC_PER_SEC;
92 tmp = readl_relaxed(pc->base + pc->data->regs.duty);
93 tmp *= pc->data->prescaler * NSEC_PER_SEC;
96 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
99 if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE)) {
122 period = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
125 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
132 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
133 if (pc->data->vop_pwm) {
154 if (pc->data->supports_lock) {
156 writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
159 writel(period, pc->base + pc->data->regs.period);
160 writel(duty, pc->base + pc->data->regs.duty);
162 if (pc->data->supports_polarity) {
176 if (pc->data->supports_lock) {
180 writel(ctrl, pc->base + pc->data->regs.ctrl);
187 u32 enable_conf = pc->data->enable_conf;
198 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
199 val &= ~pc->data->enable_conf_mask;
201 if (PWM_OUTPUT_CENTER & pc->data->enable_conf_mask) {
216 writel_relaxed(val, pc->base + pc->data->regs.ctrl);
217 if (pc->data->vop_pwm) {
243 if (state->polarity != curstate.polarity && enabled && !pc->data->supports_lock) {
338 static const struct of_device_id rockchip_pwm_dt_ids[] = {{.compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
339 {.compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
340 {.compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
341 {.compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
419 pc->data = id->data;
426 if (pc->data->supports_polarity) {
431 enable_conf = pc->data->enable_conf;
432 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);