Lines Matching refs:mux
327 /* create mux map */
334 new_map[0].data.mux.function = parent->name;
335 new_map[0].data.mux.group = np->name;
347 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", (*map)->data.mux.function, (*map)->data.mux.group,
1072 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* PWM0 IO mux M0 */
1075 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* PWM0 IO mux M1 */
1078 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* PWM1 IO mux M0 */
1081 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* PWM1 IO mux M1 */
1084 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* PWM2 IO mux M0 */
1087 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* PWM2 IO mux M1 */
1090 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* CAN0 IO mux M0 */
1093 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* CAN0 IO mux M1 */
1096 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* CAN1 IO mux M0 */
1099 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* CAN1 IO mux M1 */
1102 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* CAN2 IO mux M0 */
1105 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* CAN2 IO mux M1 */
1108 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ZERO)), /* HPDIN IO mux M0 */
1111 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ONE)), /* HPDIN IO mux M1 */
1114 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ZERO)), /* GMAC1 IO mux M0 */
1117 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ONE)), /* GMAC1 IO mux M1 */
1120 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ZERO)), /* HDMITX IO mux M0 */
1123 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ONE)), /* HDMITX IO mux M1 */
1126 PINCTRL_ROCKCHIP_ZERO)), /* I2C2 IO mux M0 */
1129 PINCTRL_ROCKCHIP_ONE)), /* I2C2 IO mux M1 */
1132 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* I2C3 IO mux M0 */
1135 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* I2C3 IO mux M1 */
1138 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* I2C4 IO mux M0 */
1141 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* I2C4 IO mux M1 */
1144 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* I2C5 IO mux M0 */
1147 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* I2C5 IO mux M1 */
1150 PINCTRL_ROCKCHIP_ZERO)), /* PWM8 IO mux M0 */
1153 PINCTRL_ROCKCHIP_ONE)), /* PWM8 IO mux M1 */
1156 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* PWM9 IO mux M0 */
1159 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* PWM9 IO mux M1 */
1162 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* PWM10 IO mux M0 */
1165 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* PWM10 IO mux M1 */
1168 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* PWM11 IO mux M0 */
1171 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* PWM11 IO mux M1 */
1174 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ZERO)), /* PWM12 IO mux M0 */
1177 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ONE)), /* PWM12 IO mux M1 */
1180 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ZERO)), /* PWM13 IO mux M0 */
1183 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ONE)), /* PWM13 IO mux M1 */
1186 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ZERO)), /* PWM14 IO mux M0 */
1189 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ONE)), /* PWM14 IO mux M1 */
1192 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ZERO)), /* PWM15 IO mux M0 */
1195 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ONE)), /* PWM15 IO mux M1 */
1198 PINCTRL_ROCKCHIP_ZERO)), /* SDMMC2 IO mux M0 */
1201 PINCTRL_ROCKCHIP_ONE)), /* SDMMC2 IO mux M1 */
1204 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* SPI0 IO mux M0 */
1207 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* SPI0 IO mux M1 */
1210 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* SPI1 IO mux M0 */
1213 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* SPI1 IO mux M1 */
1216 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* SPI2 IO mux M0 */
1219 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* SPI2 IO mux M1 */
1222 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ZERO)), /* SPI3 IO mux M0 */
1225 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ONE)), /* SPI3 IO mux M1 */
1228 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ZERO)), /* UART1 IO mux M0 */
1231 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ONE)), /* UART1 IO mux M1 */
1234 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ZERO)), /* UART2 IO mux M0 */
1237 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ONE)), /* UART2 IO mux M1 */
1240 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ZERO)), /* UART3 IO mux M0 */
1243 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ONE)), /* UART3 IO mux M1 */
1246 PINCTRL_ROCKCHIP_ZERO)), /* UART4 IO mux M0 */
1249 PINCTRL_ROCKCHIP_ONE)), /* UART4 IO mux M1 */
1252 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* UART5 IO mux M0 */
1255 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* UART5 IO mux M1 */
1258 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* UART6 IO mux M0 */
1261 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* UART6 IO mux M1 */
1264 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* UART7 IO mux M0 */
1267 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* UART7 IO mux M1 */
1270 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_TWO)), /* UART7 IO mux M2 */
1273 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ZERO)), /* UART8 IO mux M0 */
1276 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ONE)), /* UART8 IO mux M1 */
1279 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_NINE, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ZERO)), /* UART9 IO mux M0 */
1282 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_NINE, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ONE)), /* UART9 IO mux M1 */
1285 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_NINE, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_TWO)), /* UART9 IO mux M2 */
1288 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ELEVEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ZERO)), /* I2S1 IO mux M0 */
1291 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ELEVEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ONE)), /* I2S1 IO mux M1 */
1294 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ELEVEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TWO)), /* I2S1 IO mux M2 */
1297 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ZERO)), /* I2S2 IO mux M0 */
1300 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ONE)), /* I2S2 IO mux M1 */
1303 PINCTRL_ROCKCHIP_ZERO)), /* I2S3 IO mux M0 */
1306 PINCTRL_ROCKCHIP_ONE)), /* I2S3 IO mux M1 */
1309 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* PDM IO mux M0 */
1312 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* PDM IO mux M0 */
1315 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* PDM IO mux M1 */
1318 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* PDM IO mux M1 */
1321 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_TWO)), /* PDM IO mux M2 */
1324 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* PCIE20 IO mux M0 */
1327 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* PCIE20 IO mux M1 */
1330 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO)), /* PCIE20 IO mux M2 */
1333 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* PCIE30X1 IO mux M0 */
1336 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* PCIE30X1 IO mux M1 */
1339 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_TWO)), /* PCIE30X1 IO mux M2 */
1342 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SEVEN, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ZERO)), /* PCIE30X2 IO mux M0 */
1345 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SEVEN, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ONE)), /* PCIE30X2 IO mux M1 */
1348 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SEVEN, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_TWO)), /* PCIE30X2 IO mux M2 */
1351 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, int mux, u32 *loc, u32 *reg, u32 *value)
1360 if ((data->bank_num == bank->bank_num) && (data->pin == pin) && (data->func == mux)) {
1406 /* get basic quadrupel of mux registers and the correct reg inside */
1438 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1453 if (mux != RK_FUNC_GPIO) {
1454 dev_err(info->dev, "pin %d only supports a gpio mux\n", pin);
1463 * Set a new mux function for a pin.
1473 * @mux: new mux function to set
1475 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1484 ret = rockchip_verify_mux(bank, pin, mux);
1493 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1503 /* get basic quadrupel of mux registers and the correct reg inside */
1527 if (mux > mask) {
1532 if (rockchip_get_mux_route(bank, pin, mux, &route_location, &route_reg, &route_val)) {
1559 data |= (mux & mask) << bit;
1564 data |= (mux & mask) << bit;
3040 dev_err(info->dev, "pin-%d has been mux to func%d\n", pin, rc);
3123 dev_err(info->dev, "pin-%d has been mux to func%d\n", pin, rc);
3223 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
3529 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3771 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */