Lines Matching refs:data
334 new_map[0].data.mux.function = parent->name;
335 new_map[0].data.mux.group = np->name;
342 new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, grp->pins[i]);
343 new_map[i].data.configs.configs = grp->data[i].configs;
344 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
347 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", (*map)->data.mux.function, (*map)->data.mux.group,
773 struct rockchip_mux_recalced_data *data;
777 data = &ctrl->iomux_recalced[i];
778 if (data->num == bank->bank_num && data->pin == pin) {
787 *reg = data->reg;
788 *mask = data->mask;
789 *bit = data->bit;
1355 struct rockchip_mux_route_data *data;
1359 data = &ctrl->iomux_routes[i];
1360 if ((data->bank_num == bank->bank_num) && (data->pin == pin) && (data->func == mux)) {
1369 *loc = data->route_location;
1370 *reg = data->route_offset;
1371 *value = data->route_val;
1482 u32 data, rmask, route_location, route_reg, route_val;
1553 ret = regmap_read(regmap, reg, &data);
1558 data &= ~(mask << bit);
1559 data |= (mux & mask) << bit;
1560 ret = regmap_write(regmap, reg, data);
1562 data = (mask << (bit + PINCTRL_ROCKCHIP_SIXTEEN));
1563 rmask = data | (data >> PINCTRL_ROCKCHIP_SIXTEEN);
1564 data |= (mux & mask) << bit;
1565 ret = regmap_update_bits(regmap, reg, rmask, data);
2387 u32 data, temp, rmask_bits;
2406 ret = regmap_read(regmap, reg, &data);
2417 * the bit data[15] contains bit 0 of the value
2420 data >>= PINCTRL_ROCKCHIP_FIFTEEN;
2423 data |= temp;
2425 return rockchip_perpin_drv_list[drv_type][data];
2447 ret = regmap_read(regmap, reg, &data);
2452 data >>= bit;
2453 data &= (PINCTRL_ROCKCHIP_ONE << rmask_bits) - PINCTRL_ROCKCHIP_ONE;
2455 return rockchip_perpin_drv_list[drv_type][data];
2464 u32 data, rmask, rmask_bits, temp;
2508 * over 2 registers, the bit data[15] contains bit 0
2511 data = (ret & 0x1) << PINCTRL_ROCKCHIP_FIFTEEN;
2515 data |= BIT(PINCTRL_ROCKCHIP_THIRTYONE);
2516 ret = regmap_update_bits(regmap, reg, rmask, data);
2549 data = ((PINCTRL_ROCKCHIP_ONE << rmask_bits) - PINCTRL_ROCKCHIP_ONE) << (bit + PINCTRL_ROCKCHIP_SIXTEEN);
2550 rmask = data | (data >> PINCTRL_ROCKCHIP_SIXTEEN);
2551 data |= (ret << bit);
2553 ret = regmap_update_bits(regmap, reg, rmask, data);
2575 data = ((PINCTRL_ROCKCHIP_ONE << rmask_bits) - PINCTRL_ROCKCHIP_ONE) << PINCTRL_ROCKCHIP_SIXTEEN;
2576 rmask = data | (data >> PINCTRL_ROCKCHIP_SIXTEEN);
2577 data |= (PINCTRL_ROCKCHIP_ONE << (strength + PINCTRL_ROCKCHIP_ONE)) - PINCTRL_ROCKCHIP_ONE;
2579 ret = regmap_update_bits(regmap, reg, rmask, data);
2600 u32 data;
2609 ret = regmap_read(regmap, reg, &data);
2617 return !(data & BIT(bit)) ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT : PIN_CONFIG_BIAS_DISABLE;
2629 data >>= bit;
2630 data &= (PINCTRL_ROCKCHIP_ONE << RK3188_PULL_BITS_PER_PIN) - PINCTRL_ROCKCHIP_ONE;
2632 return rockchip_pull_list[pull_type][data];
2646 u32 data, rmask;
2660 data = BIT(bit + PINCTRL_ROCKCHIP_SIXTEEN);
2662 data |= BIT(bit);
2664 ret = regmap_write(regmap, reg, data);
2701 data = ((1 << RK3188_PULL_BITS_PER_PIN) - PINCTRL_ROCKCHIP_ONE) << (bit + PINCTRL_ROCKCHIP_SIXTEEN);
2702 rmask = data | (data >> PINCTRL_ROCKCHIP_SIXTEEN);
2703 data |= (ret << bit);
2705 ret = regmap_update_bits(regmap, reg, rmask, data);
2769 u32 data;
2776 ret = regmap_read(regmap, reg, &data);
2781 data >>= bit;
2784 return data & ((PINCTRL_ROCKCHIP_ONE << RK3568_SCHMITT_BITS_PER_PIN) - PINCTRL_ROCKCHIP_ONE);
2789 return data & 0x1;
2799 u32 data, rmask;
2811 data = ((PINCTRL_ROCKCHIP_ONE << RK3568_SCHMITT_BITS_PER_PIN) - PINCTRL_ROCKCHIP_ONE)
2813 rmask = data | (data >> PINCTRL_ROCKCHIP_SIXTEEN);
2814 data |= ((enable ? 0x2 : 0x1) << bit);
2817 data = BIT(bit + PINCTRL_ROCKCHIP_SIXTEEN) | (enable << bit);
2822 return regmap_update_bits(regmap, reg, rmask, data);
2860 u32 data;
2867 ret = regmap_read(regmap, reg, &data);
2872 data >>= bit;
2873 return data & 0x1;
2883 u32 data, rmask;
2893 data = BIT(bit + PINCTRL_ROCKCHIP_SIXTEEN) | (speed << bit);
2896 return regmap_update_bits(regmap, reg, rmask, data);
2932 const struct rockchip_pin_config *data = info->groups[group].data;
2944 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, data[cnt].func);
2952 for (cnt--; cnt >= 0 && !data[cnt].func; cnt--) {
3237 grp->data = devm_kcalloc(info->dev, grp->npins, sizeof(struct rockchip_pin_config), GFP_KERNEL);
3238 if (!grp->pins || !grp->data) {
3253 grp->data[j].func = be32_to_cpu(*list++);
3261 ret = pinconf_generic_parse_dt_config(np_config, NULL, &grp->data[j].configs, &grp->data[j].nconfigs);
3399 /* retrieve the soc specific data */
3409 ctrl = (struct rockchip_pin_ctrl *)match->data;
3561 /* SoC data specially handle */
3563 /* rk3308 SoC data initialize */
3629 dev_err(dev, "driver data not available\n");
4100 {.compatible = "rockchip,px30-pinctrl", .data = &px30_pin_ctrl},
4101 {.compatible = "rockchip,rv1108-pinctrl", .data = &rv1108_pin_ctrl},
4102 {.compatible = "rockchip,rv1126-pinctrl", .data = &rv1126_pin_ctrl},
4103 {.compatible = "rockchip,rk1808-pinctrl", .data = &rk1808_pin_ctrl},
4104 {.compatible = "rockchip,rk2928-pinctrl", .data = &rk2928_pin_ctrl},
4105 {.compatible = "rockchip,rk3036-pinctrl", .data = &rk3036_pin_ctrl},
4106 {.compatible = "rockchip,rk3066a-pinctrl", .data = &rk3066a_pin_ctrl},
4107 {.compatible = "rockchip,rk3066b-pinctrl", .data = &rk3066b_pin_ctrl},
4108 {.compatible = "rockchip,rk3128-pinctrl", .data = (void *)&rk3128_pin_ctrl},
4109 {.compatible = "rockchip,rk3188-pinctrl", .data = &rk3188_pin_ctrl},
4110 {.compatible = "rockchip,rk3228-pinctrl", .data = &rk3228_pin_ctrl},
4111 {.compatible = "rockchip,rk3288-pinctrl", .data = &rk3288_pin_ctrl},
4112 {.compatible = "rockchip,rk3308-pinctrl", .data = &rk3308_pin_ctrl},
4113 {.compatible = "rockchip,rk3328-pinctrl", .data = &rk3328_pin_ctrl},
4114 {.compatible = "rockchip,rk3368-pinctrl", .data = &rk3368_pin_ctrl},
4115 {.compatible = "rockchip,rk3399-pinctrl", .data = &rk3399_pin_ctrl},
4116 {.compatible = "rockchip,rk3568-pinctrl", .data = &rk3568_pin_ctrl},