Lines Matching defs:mask
358 u32 index, mask;
361 mask = 1 << (index % IRQ_HW_IRQ_VALUE);
369 return !!(readl_relaxed(base + offset + (index / IRQ_HW_IRQ_VALUE) * IRQ_HW_IRQ_VALUE_MUL) & mask);
376 u32 index, mask;
379 mask = 1 << (index % 0x20);
389 writel_relaxed(mask, base + offset + (index / IRQ_HW_IRQ_VALUE) * IRQ_HW_IRQ_VALUE_MUL);
1022 /* Set priority mask register */
1146 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, unsigned long cluster_id)
1155 next_cpu = cpumask_next(cpu, mask);
1188 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
1202 for_each_cpu(cpu, mask)
1207 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
1641 .mask = 0xffffffff,
1647 .mask = 0xffffffff,
1660 .mask = 0xe8f00fff,
1719 * be in the non-secure range, we use a different PMR value to mask IRQs
1904 cpumask_set_cpu(cpu, &part->mask);