Lines Matching defs:base

222 static void gic_do_wait_for_rwp(void __iomem *base, u32 bit)

226     while (readl_relaxed(base + GICD_CTLR) & bit) {

357     void __iomem *base;

364         base = gic_data_rdist_sgi_base();

366         base = gic_data.dist_base;

369     return !!(readl_relaxed(base + offset + (index / IRQ_HW_IRQ_VALUE) * IRQ_HW_IRQ_VALUE_MUL) & mask);

375     void __iomem *base;

382         base = gic_data_rdist_sgi_base();

385         base = gic_data.dist_base;

389     writel_relaxed(mask, base + offset + (index / IRQ_HW_IRQ_VALUE) * IRQ_HW_IRQ_VALUE_MUL);

481     void __iomem *base = gic_dist_base(d);

486     writeb_relaxed(prio, base + offset + index);

596     void __iomem *base;

612         base = gic_data_rdist_sgi_base();

615         base = gic_data.dist_base;

621     ret = gic_configure_irq(index, type, base + offset, rwp_wait);

804     void __iomem *base = gic_data.dist_base;

808     writel_relaxed(0, base + GICD_CTLR);

818         writel_relaxed(~0, base + GICD_IGROUPR + i / 0x8);

823         writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 0x8);

824         writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 0x8);

828         writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 0x8);

832         writel_relaxed(0, base + GICD_ICFGRnE + i / 0x4);

836         writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i);

840     gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp);

849     writel_relaxed(val, base + GICD_CTLR);

857         gic_write_irouter(affinity, base + GICD_IROUTER + i * 0x8);

861         gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 0x8);

2117     /* Collect redistributor base addresses in GICR entries */

2137      * If GICC is enabled and has valid gicr base address, then it means

2138      * GICR base is presented via GICC

2285     /* Get distributor base address */