irq-gic-v3-its.c - OpenGrok cross reference for /device/soc/rockchip/common/sdk

Lines Matching refs:hwirq
230     return d->hwirq - its_dev->event_map.lpi_base;

1378     irq_hw_number_t hwirq;

1384         hwirq = map->vintid;

1391         hwirq = d->hwirq;

1394     cfg = va + hwirq - 0x2000;

1434         val = d->hwirq;

1903     its_send_mapti(its_dev, d->hwirq, event);

3475 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)

3485     *hwirq = dev->event_map.lpi_base + idx;

3546 static int its_irq_gic_domain_alloc(struct irq_domain *domain, unsigned int virq, irq_hw_number_t hwirq)

3554         fwspec.param[1] = hwirq;

3559         fwspec.param[0] = hwirq;

3574     irq_hw_number_t hwirq;

3578     err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);

3589         err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);

3594         irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, &its_irq_chip, its_dev);

3598         pr_debug("ID:%d pID:%d vID:%d\n", (int)(hwirq + i - its_dev->event_map.lpi_base), (int)(hwirq + i), virq + i);

3620     its_send_mapti(its_dev, d->hwirq, event);

3967         gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR);

4195     desc.its_vsgi_cmd.sgi = d->hwirq;

4196     desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority;

4197     desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled;

4198     desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group;

4213     vpe->sgi_config[d->hwirq].enabled = false;

4221     vpe->sgi_config[d->hwirq].enabled = true;

4248         val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq);

4307     *val = !!(status & (1 << d->hwirq));

4319             vpe->sgi_config[d->hwirq].priority = info->priority;

4320             vpe->sgi_config[d->hwirq].group = info->group;

4385     vpe->sgi_config[d->hwirq].enabled = false;

4463         clear_bit(data->hwirq, vm->db_bitmap);