Lines Matching defs:to
54 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
55 * deal with (one configuration byte per interrupt). PENDBASE has to
65 * Collection structure - just an ID, and a redistributor address to
66 * ping. We use one per CPU as a bag of interrupts assigned to this
90 * list of devices writing to it.
92 * dev_alloc_lock has to be taken for device allocations, while the
93 * spinlock must be taken to parse data structures such as the device
139 /* Convert page order to size in bytes */
154 * The ITS view of a device - belongs to an ITS, owns an interrupt
318 * ITS command descriptors - parameters to be encoded in a command
944 /* This is incredibly unlikely to happen, unless the ITS locks up. */
995 * Make sure the commands written to memory are observable by
1005 static int its_wait_for_range_completion(struct its_node *its, u64 prev_idx, struct its_cmd_block *to)
1011 to_idx = its_cmd_ptr_to_offset(its, to);
1285 * its_list "feature", we need to make sure that all ITSs
1287 * to guarantee this is to make vmovp a serialization point.
1399 * Make the above write visible to the redistributors.
1437 /* Target the redistributor this LPI is currently routed to */
1468 * GICv4.1 does away with the per-LPI nonsense, nothing to do
1482 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1483 * value or to 1023, depending on the enable bit. But that
1486 * to the /same/ vPE, using this opportunity to adjust the
1575 * node mask (and the online mask, just to be safe).
1587 * ITS placed next to two NUMA nodes.
1617 /* If we cannot cross sockets, limit the search to that node */
1730 * (a) Either we have a GICv4.1, and all vPEs have to be mapped at all times
1771 /* Map the VPE to the first possible CPU */
1848 /* Write out the property to the prop table */
1877 /* Copy our mapping information to the incoming request */
1987 * lpi_range_list contains ranges of LPIs that are to available to
1992 * To free a range of LPIs, add a free range to the list, sort it and
1993 * merge the result if the new range happens to be adjacent to an
2089 * the list is the right thing to do in that case as well.
2254 pr_err("Failed to allocate PROPBASE\n");
2329 /* Convert 52bit PA to 48bit field */
2365 * to be the only thing this redistributor
2407 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
2411 * table by reading bit at offset '62' after writing '1' to it.
2418 * The size of the lvl2 table is equal to ITS page size
2430 * Allocate as many entries as required to fit the
2466 * the resulting affinity. We then use that to see if this match
2794 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2801 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2806 /* Ensure updated table contents are visible to RD hardware */
2837 * so. Otherwise, we have to go through the allocation process. We
2880 * (which we want to print in debug cases...)
2899 /* Number of L2 pages required to cover the VPEID space */
2902 /* Number of L1 pages to point to the L2 pages */
3025 pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
3157 * It's possible for CPU to receive VLPIs before it is
3161 * So we initialize IDbits to known value to avoid VLPI drop.
3164 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n", smp_processor_id(), val);
3209 * We now have to bind each collection to its target
3308 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
3315 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
3320 /* Ensure updated table contents are visible to ITS hardware */
3345 * could try and only do it on ITSs corresponding to devices
3368 /* Non v4.1? No need to iterate RDs and go back early. */
3457 /* Map device to its ITT */
3501 * usefulness to upper layers that definitely know that they
3521 * another alias (PCI bridge of some sort). No need to
3619 /* Map the GIC IRQ and event to the device */
3680 * likely), the only way to perform an invalidate is to use a fake
3681 * device to issue an INV command, implying that the LPI has first
3682 * been mapped to some event on that device. Since this is not exactly
3683 * cheap, we try to keep that mapping around as long as possible, and
3688 * GICv4.1, on the other hand, mandates that we're able to invalidate
3689 * by writing to a MMIO register. It doesn't implement the whole of
3691 * even have to invalidate anything, as the redistributor can be told
3692 * whether to generate a doorbell or not (we thus leave it enabled,
3697 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3726 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3742 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3766 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
3771 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3790 target_col = &vpe_proxy.dev->its->collections[to];
3792 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
3805 * we can and only do it if we really have to. Also, if mapped
3806 * into the proxy device, we need to move the doorbell
3807 * interrupt to its new location.
3810 * *other interrupts* such as all the vLPIs that are routed to
3811 * this vPE. This means that the irq_desc lock is not enough to
3824 * GICv4.1 allows us to skip VMOVP if moving to a cpu whose RD
3875 * would be able to read its coarse map pretty quickly anyway,
3910 * Sending a VINVALL to a single ITS is enough, as all
3911 * we need is to reach the redistributors.
3978 * We need to unmask the LPI, which is described by the parent
4064 * GICv4.1 wants doorbells to be invalidated using the
4065 * INVDB command in order to be broadcast to all RDs. Send
4066 * it to the first valid ITS, and let the HW do its magic.
4109 * vPE is going to block: make the vPE non-resident with
4114 * Note the locking to deal with the concurrent update of
4202 * GICv4.1 allows us to send VSGI commands to any ITS as long as the
4274 * happen, or we'll talk to the wrong redistributor. This is
4275 * identical to what happens with vLPIs.
4292 pr_err_ratelimited("Unable to get SGI status\n");
4361 /* Nothing to do */
4378 * - To change the configuration, CLEAR must be set to false,
4380 * - To clear the pending bit, CLEAR must be set to true, leaving
4549 /* Map the VPE to the first possible CPU */
4604 * GIC architecture specification requires the ITS to be both
4605 * disabled and quiescent for writes to GITS_BASER<n> or
4606 * GITS_CBASER to not have UNPREDICTABLE results.
4612 /* Disable the generation of all interrupts to this ITS */
4672 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
4785 pr_err("ITS@%pa: failed to quiesce: %d\n", &its->phys_base, err);
4822 * Make sure that the ITS is disabled. If it fails to quiesce,
4823 * don't restore it since writing to CBASER or BASER<n>
4824 * registers is undefined according to the GIC v3 ITS
4832 pr_err("ITS@%pa: failed to quiesce on resume: %d\n", &its->phys_base, ret);
4839 * Writing CBASER resets CREADR to 0, so make CWRITER and
4945 * This is assumed to be done early enough that we're
4946 * guaranteed to be single-threaded, hence no
4986 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
4999 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
5159 * If coming via a CPU hotplug event, we don't need to disable
5160 * LPIs before trying to re-enable them. They are already
5163 * If running with preallocated tables, there is nothing to do.
5170 * From that point on, we only try to do some damage control.
5179 /* Make sure any change to GICR_CTLR is observable by the GIC */
5184 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
5185 * Error out if we time out waiting for RWP to clear.
5197 * After it has been written to 1, it is IMPLEMENTATION
5199 * cleared to 0. Error out if clearing the bit failed.
5202 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
5336 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
5377 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", &res.start);
5383 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", &res.start,