Lines Matching defs:gc
135 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
137 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
145 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
147 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
177 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
179 return rockchip_gpio_set_direction(gc, offset, true);
182 static int rockchip_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
184 rockchip_gpio_set(gc, offset, value);
186 return rockchip_gpio_set_direction(gc, offset, false);
189 static int rockchip_gpio_set_debounce(struct gpio_chip *gc, unsigned int offset, unsigned int debounce)
191 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
256 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, unsigned long config)
275 rockchip_gpio_set_debounce(gc, offset, debounce);
290 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
292 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
378 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
379 struct rockchip_pin_bank *bank = gc->private;
461 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
462 struct rockchip_pin_bank *bank = gc->private;
464 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
465 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
470 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
471 struct rockchip_pin_bank *bank = gc->private;
473 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
479 struct irq_chip_generic *gc;
495 gc = irq_get_domain_generic_chip(bank->domain, 0);
497 gc->reg_writel = gpio_writel_v2;
498 gc->reg_readl = gpio_readl_v2;
500 gc->reg_base = bank->reg_base;
501 gc->private = bank;
502 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
503 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
504 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
505 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
506 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
507 gc->chip_types[0].chip.irq_enable = irq_gc_mask_clr_bit;
508 gc->chip_types[0].chip.irq_disable = irq_gc_mask_set_bit;
509 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
510 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
511 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
512 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
513 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
523 gc->mask_cache = 0xffffffff;
532 struct gpio_chip *gc;
537 gc = &bank->gpio_chip;
538 gc->base = bank->pin_base;
539 gc->ngpio = bank->nr_pins;
540 gc->label = bank->name;
541 gc->parent = bank->dev;
543 gc->of_node = of_node_get(bank->of_node);
546 ret = gpiochip_add_data(gc, bank);
548 dev_err(bank->dev, "failed to add gpiochip %s, %d\n", gc->label, ret);
575 ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0, gc->base, gc->ngpio);