Lines Matching refs:port
36 struct UartPl011Port *port = NULL;
44 port = (struct UartPl011Port *)udd->private;
45 status = OSAL_READW(port->physBase + UART_MIS);
48 fr = OSAL_READB(port->physBase + UART_FR);
52 buf[count++] = OSAL_READB(port->physBase + UART_DR);
64 OSAL_WRITEW(0xFFFF, port->physBase + UART_CLR);
68 static void Pl011ConfigBaudrate(const struct UartDriverData *udd, const struct UartPl011Port *port)
87 OSAL_WRITEL(divider, port->physBase + UART_IBRD);
88 OSAL_WRITEL(fraction, port->physBase + UART_FBRD);
157 static void Pl011ConfigLCRH(const struct UartDriverData *udd, const struct UartPl011Port *port, uint32_t lcrh)
168 OSAL_WRITEB(lcrh, port->physBase + UART_LCR_H);
175 struct UartPl011Port *port = NULL;
177 port = (struct UartPl011Port *)udd->private;
178 if (port == NULL) {
179 HDF_LOGE("%s: port is NULL", __func__);
183 cr = OSAL_READW(port->physBase + UART_CR);
185 lcrh = OSAL_READW(port->physBase + UART_LCR_H);
187 OSAL_WRITEW(0, port->physBase + UART_CR);
200 OSAL_WRITEB(lcrh, port->physBase + UART_LCR_H);
203 OSAL_WRITEW(cr, port->physBase + UART_CR);
206 Pl011ConfigBaudrate(udd, port);
209 Pl011ConfigLCRH(udd, port, lcrh);
213 OSAL_WRITEW(cr, port->physBase + UART_CR);
221 struct UartPl011Port *port = NULL;
227 port = (struct UartPl011Port *)udd->private;
228 if (port == NULL) {
229 HDF_LOGE("%s: port is null", __func__);
237 OSAL_WRITEW(0, port->physBase + UART_CR);
238 OSAL_WRITEW(0xFF, port->physBase + UART_RSR);
240 OSAL_WRITEW(0xFFFF, port->physBase + UART_CLR);
242 OSAL_WRITEW(0x0, port->physBase + UART_IMSC);
244 OSAL_WRITEW(UART_IFLS_RX4_8 | UART_IFLS_TX7_8, port->physBase + UART_IFLS);
246 if (!(port->flags & PL011_FLG_IRQ_REQUESTED)) {
247 ret = OsalRegisterIrq(port->irqNum, 0, Pl011Irq, "uart_pl011", udd);
249 port->flags |= PL011_FLG_IRQ_REQUESTED;
251 OSAL_WRITEW(UART_IMSC_RX | UART_IMSC_TIMEOUT, port->physBase + UART_IMSC);
255 cr = OSAL_READW(port->physBase + UART_CR);
257 OSAL_WRITEL(cr, port->physBase + UART_CR);
265 struct UartPl011Port *port = NULL;
271 port = (struct UartPl011Port *)udd->private;
272 if (port == NULL) {
273 HDF_LOGE("%s: port is null", __func__);
276 OSAL_WRITEW(0, port->physBase + UART_IMSC);
277 OSAL_WRITEW(0xFFFF, port->physBase + UART_CLR);
278 if (port->flags & PL011_FLG_IRQ_REQUESTED) {
279 OsalUnregisterIrq(port->irqNum, udd);
280 port->flags &= ~PL011_FLG_IRQ_REQUESTED;
283 reg_tmp = OSAL_READW(port->physBase + UART_CR);
287 OSAL_WRITEW(reg_tmp, port->physBase + UART_CR);
290 reg_tmp = OSAL_READW(port->physBase + UART_LCR_H);
293 OSAL_WRITEW(reg_tmp, port->physBase + UART_LCR_H);
304 struct UartPl011Port *port = NULL;
310 port = (struct UartPl011Port *)udd->private;
311 if (port == NULL) {
312 HDF_LOGE("%s: port is null", __func__);
316 (void)UartPutsReg(port->physBase, buf, count, UART_WITH_LOCK);
323 struct UartPl011Port *port = NULL;
329 port = (struct UartPl011Port *)udd->private;
330 if (port == NULL) {
331 HDF_LOGE("%s: port is null", __func__);
336 fr = OSAL_READB(port->physBase + UART_FR);