Lines Matching refs:regBase
44 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL);
52 TimerHi35xxRegWrite(value, info->regBase + HI35XX_TIMERx_CONTROL);
53 TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL);
61 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL);
70 TimerHi35xxRegWrite(value, info->regBase + HI35XX_TIMERx_CONTROL);
78 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL);
97 TimerHi35xxRegWrite(value, info->regBase + HI35XX_TIMERx_CONTROL);
98 TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL);
106 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL);
114 TimerHi35xxRegWrite(value, info->regBase + HI35XX_TIMERx_CONTROL);
122 TimerHi35xxRegWrite(0x0, info->regBase + HI35XX_TIMERx_INTCLR);
129 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL);
137 TimerHi35xxRegWrite(value, info->regBase + HI35XX_TIMERx_CONTROL);
146 TimerHi35xxRegWrite(value, info->regBase + HI35XX_TIMERx_LOAD);
152 TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_LOAD);
153 TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_VALUE);
154 TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL);
155 TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_INTCLR);
156 TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_RIS);
157 TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_MIS);
158 TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_BGLOAD);
164 {"HI35XX_TIMERx_LOAD", PLATFORM_DUMPER_REGISTERB, (void *)(info->regBase + HI35XX_TIMERx_LOAD)},
165 {"HI35XX_TIMERx_VALUE", PLATFORM_DUMPER_REGISTERB, (void *)(info->regBase + HI35XX_TIMERx_VALUE)},
166 {"HI35XX_TIMERx_CONTROL", PLATFORM_DUMPER_REGISTERB, (void *)(info->regBase + HI35XX_TIMERx_CONTROL)},
167 {"HI35XX_TIMERx_INTCLR", PLATFORM_DUMPER_REGISTERB, (void *)(info->regBase + HI35XX_TIMERx_INTCLR)},
168 {"HI35XX_TIMERx_RIS", PLATFORM_DUMPER_REGISTERB, (void *)(info->regBase + HI35XX_TIMERx_RIS)},
169 {"HI35XX_TIMERx_MIS", PLATFORM_DUMPER_REGISTERB, (void *)(info->regBase + HI35XX_TIMERx_MIS)},
170 {"HI35XX_TIMERx_BGLOAD", PLATFORM_DUMPER_REGISTERB, (void *)(info->regBase + HI35XX_TIMERx_BGLOAD)},
182 volatile uint8_t *regBase =
184 if (regBase == NULL) {
188 uint32_t value = TimerHi35xxRegRead(regBase);
205 TimerHi35xxRegWrite(value, regBase);
206 TimerHi35xxRegRead(regBase);
207 OsalIoUnmap((void *)regBase);
208 regBase = NULL;
287 OSAL_WRITEL(value, info->regBase + HI35XX_TIMERx_LOAD);
397 if (info->regBase != NULL) {
398 OsalIoUnmap((void *)info->regBase);
399 info->regBase = NULL;
428 TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL);
480 info->regBase = OsalIoRemap(tmp, TIMER_MAX_REG_SIZE);
481 if (info->regBase == NULL) {