Lines Matching refs:HiRtcSpiWrite
90 HDF_LOGE("HiRtcSpiWrite: spi busy!");
97 static uint32_t HiRtcSpiWrite(struct RtcConfigInfo *rtcInfo, uint8_t regAdd, uint8_t value)
178 ret = HiRtcSpiWrite(rtcInfo, RTC_LORD, (~(RTC_LOCK_BYPASS_MASK)) & value);
189 ret = HiRtcSpiWrite(rtcInfo, RTC_LORD, (value | RTC_LOCK_MASK));
252 ret = HiRtcSpiWrite(rtcInfo, regAddr->millisecondAddr, millisecond);
256 ret = HiRtcSpiWrite(rtcInfo, regAddr->secondAddr, time->second);
260 ret = HiRtcSpiWrite(rtcInfo, regAddr->minuteAddr, time->minute);
264 ret = HiRtcSpiWrite(rtcInfo, regAddr->hourAddr, time->hour);
268 ret = HiRtcSpiWrite(rtcInfo, regAddr->dayLowAddr, (day & 0xFF)); /* 0xFF:mask */
272 ret = HiRtcSpiWrite(rtcInfo, regAddr->dayHighAddr, (day >> SHIFT_BYTE)); /* 8:[15:8] for day high bit */
306 ret = HiRtcSpiWrite(rtcInfo, RTC_LORD, (value | RTC_LOAD_MASK));
421 ret = HiRtcSpiWrite(rtcInfo, RTC_MSC, (value | RTC_MSC_TIME_MASK));
423 ret = HiRtcSpiWrite(rtcInfo, RTC_MSC, (value & (~RTC_MSC_TIME_MASK)));
480 ret = HiRtcSpiWrite(rtcInfo, RTC_FREQ_H, highFreq);
481 ret |= HiRtcSpiWrite(rtcInfo, RTC_FREQ_L, lowFreq);
500 ret = HiRtcSpiWrite(rtcInfo, RTC_POR_N, 0);
506 ret = HiRtcSpiWrite(rtcInfo, RTC_CLK, RTC_CLK_OUT_SEL);
547 return HiRtcSpiWrite(rtcInfo, g_usrRegAddr[usrDefIndex], value);
738 ret |= HiRtcSpiWrite(rtcInfo, rtcInfo->anaCtrlAddr, RTC_ANA_CTRL_ENABLE);
743 ret |= HiRtcSpiWrite(rtcInfo, rtcInfo->lockAddr.lock3Addr, RTC_LOCK_ORDER2);
744 ret |= HiRtcSpiWrite(rtcInfo, rtcInfo->lockAddr.lock2Addr, RTC_LOCK_ORDER2);
745 ret |= HiRtcSpiWrite(rtcInfo, rtcInfo->lockAddr.lock1Addr, RTC_LOCK_ORDER1);
746 ret |= HiRtcSpiWrite(rtcInfo, rtcInfo->lockAddr.lock0Addr, RTC_LOCK_ORDER0);
747 ret |= HiRtcSpiWrite(rtcInfo, rtcInfo->anaCtrlAddr, RTC_ANA_CTRL_ORDER);
764 ret |= HiRtcSpiWrite(rtcInfo, RTC_MSC, RTC_MSC_ENABLE);
765 ret |= HiRtcSpiWrite(rtcInfo, RTC_SAR_CTRL, RTC_UV_CTRL_ENABLE);
767 ret |= HiRtcSpiWrite(rtcInfo, RTC_FREQ_H, FREQ_H_DEFAULT);
768 ret |= HiRtcSpiWrite(rtcInfo, RTC_FREQ_L, FREQ_L_DEFAULT);