Lines Matching refs:host
33 static void SdhciDumpregs(struct SdhciHost *host)
35 HDF_LOGE(": =========== DUMP (host%u) REGISTER===========", host->hostId);
37 SdhciReadl(host, SDMASA_R), SdhciReadw(host, HOST_VERSION_R));
39 SdhciReadw(host, BLOCKSIZE_R), SdhciReadw(host, BLOCKCOUNT_R));
41 SdhciReadl(host, ARGUMENT_R), SdhciReadw(host, XFER_MODE_R));
43 SdhciReadl(host, PSTATE_R), SdhciReadb(host, HOST_CTRL1_R));
45 SdhciReadb(host, PWR_CTRL_R), SdhciReadb(host, BLOCK_GAP_CTRL_R));
47 SdhciReadb(host, WUP_CTRL_R), SdhciReadw(host, CLK_CTRL_R));
49 SdhciReadb(host, TOUT_CTRL_R), SdhciReadl(host, NORMAL_INT_STAT_R));
51 SdhciReadl(host, NORMAL_INT_STAT_EN_R), SdhciReadl(host, NORMAL_INT_SIGNAL_EN_R));
53 SdhciReadw(host, AUTO_CMD_STAT_R), SdhciReadw(host, SLOT_INT_STATUS_R));
55 SdhciReadl(host, CAPABILITIES1_R), SdhciReadl(host, CAPABILITIES2_R));
57 SdhciReadw(host, CMD_R), SdhciReadl(host, CURR_CAPBILITIES1_R), (SdhciReadw(host, CMD_R) >> 8) & 0x1f);
59 SdhciReadl(host, RESP01_R + 0x4), SdhciReadl(host, RESP01_R));
61 SdhciReadl(host, RESP01_R + 0xC), SdhciReadl(host, RESP01_R + 0x8));
62 HDF_LOGE(": Host ctl2: 0x%04x", SdhciReadw(host, HOST_CTRL2_R));
64 SdhciReadw(host, EMMC_CTRL_R), SdhciReadl(host, MULTI_CYCLE_R));
65 if (host->flags & SDHCI_USE_64BIT_ADMA) {
66 HDF_LOGE(": ADMA Err: 0x%08x\n", SdhciReadl(host, ADMA_ERR_STAT_R));
68 SdhciReadl(host, ADMA_SA_LOW_R), SdhciReadl(host, ADMA_SA_HIGH_R));
69 } else if (host->flags & SDHCI_USE_ADMA) {
71 SdhciReadl(host, ADMA_ERR_STAT_R), SdhciReadl(host, ADMA_SA_LOW_R));
96 static void SdhciEnablePlugIrq(struct SdhciHost *host, uint32_t irq)
98 SdhciWritel(host, irq, NORMAL_INT_STAT_EN_R);
99 SdhciWritel(host, irq, NORMAL_INT_SIGNAL_EN_R);
102 static void SdhciSetCardDetection(struct SdhciHost *host, bool enable)
106 if (host->mmc->caps.bits.nonremovable > 0 ||
107 host->quirks.bits.forceSWDetect > 0 ||
108 host->quirks.bits.brokenCardDetection > 0) {
113 present = SdhciReadl(host, PSTATE_R) & SDHCI_CARD_PRESENT;
114 host->irqEnable |= (present ? SDHCI_INTERRUPT_CARD_REMOVE : SDHCI_INTERRUPT_CARD_INSERT);
116 host->irqEnable &= (~(SDHCI_INTERRUPT_CARD_REMOVE | SDHCI_INTERRUPT_CARD_INSERT));
120 static void SdhciEnableCardDetection(struct SdhciHost *host)
122 SdhciSetCardDetection(host, true);
123 SdhciWritel(host, host->irqEnable, NORMAL_INT_STAT_EN_R);
124 SdhciWritel(host, host->irqEnable, NORMAL_INT_SIGNAL_EN_R);
127 static void SdhciReset(struct SdhciHost *host, uint32_t mask)
132 SdhciWriteb(host, mask, SW_RST_R);
135 reg = SdhciReadb(host, SW_RST_R);
142 HDF_LOGE("host%u: Reset 0x%x never completed.", host->hostId, mask);
143 SdhciDumpregs(host);
146 static void SdhciDoReset(struct SdhciHost *host, uint32_t mask)
148 SdhciReset(host, mask);
151 host->presetEnabled = false;
152 host->clock = 0;
156 static void SdhciSetTransferMode(struct SdhciHost *host, struct MmcCmd *cmd)
161 mode = SdhciReadw(host, XFER_MODE_R);
162 SdhciWritew(host, (mode & (~(SDHCI_TRNS_AUTO_CMD12 | SDHCI_TRNS_AUTO_CMD23))), XFER_MODE_R);
169 if ((host->mmc->devType == MMC_DEV_SD && (MmcCntlrSdSupportCmd23(host->mmc) == false)) ||
170 (host->mmc->devType == MMC_DEV_EMMC && (MmcCntlrEmmcSupportCmd23(host->mmc) == false))) {
173 if ((host->flags & SDHCI_AUTO_CMD23)) {
175 SdhciWritel(host, cmd->data->blockNum, SDHCI_ARGUMENT2);
176 } else if ((host->flags & SDHCI_AUTO_CMD12) > 0) {
185 if ((host->flags & SDHCI_REQ_USE_DMA) > 0) {
188 SdhciWritew(host, mode, XFER_MODE_R);
191 static void SdhciTaskletFinish(struct SdhciHost *host)
193 struct MmcCmd *cmd = host->cmd;
195 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
197 SdhciDoReset(host, SDHCI_RESET_CMD);
198 SdhciDoReset(host, SDHCI_RESET_DATA);
201 host->cmd = NULL;
202 (void)SDHCI_EVENT_SIGNAL(&host->sdhciEvent, SDHCI_PEND_REQUEST_DONE);
234 static void SdhciSetDmaConfig(struct SdhciHost *host)
238 if (host->version < SDHCI_HOST_SPEC_200) {
242 ctrl = SdhciReadb(host, HOST_CTRL1_R);
244 if ((host->flags & SDHCI_REQ_USE_DMA) && (host->flags & SDHCI_USE_ADMA)) {
245 if (host->flags & SDHCI_USE_64BIT_ADMA) {
253 SdhciWriteb(host, ctrl, HOST_CTRL1_R);
256 static void SdhciSetTransferIrqs(struct SdhciHost *host)
261 if (host->flags & SDHCI_REQ_USE_DMA) {
262 host->irqEnable = (host->irqEnable & ~pioIrqs) | dmaIrqs;
264 host->irqEnable = (host->irqEnable & ~dmaIrqs) | pioIrqs;
266 SdhciEnablePlugIrq(host, host->irqEnable);
269 static void SdhciSetBlkSizeReg(struct SdhciHost *host, uint32_t blksz, uint32_t sdmaBoundary)
271 if (host->flags & SDHCI_USE_ADMA) {
272 SdhciWritel(host, SDHCI_MAKE_BLKSZ(7, blksz), BLOCKSIZE_R);
274 SdhciWritel(host, SDHCI_MAKE_BLKSZ(sdmaBoundary, blksz), BLOCKSIZE_R);
278 static void SdhciAdmaConfig(struct SdhciHost *host)
280 SdhciWritel(host, 0, (uintptr_t)ADMA_SA_HIGH_R);
281 SdhciWritel(host, VMM_TO_DMA_ADDR((uintptr_t)host->admaDesc), (uintptr_t)ADMA_SA_LOW_R);
284 static void SdhciSetAdmaDesc(struct SdhciHost *host, char *desc, dma_addr_t addr, uint16_t len, uint16_t cmd)
291 if (host->flags & SDHCI_USE_64BIT_ADMA) {
307 static int32_t SdhciAdmaTablePre(struct SdhciHost *host, struct MmcData *data)
318 admaDesc = host->admaDesc;
319 (void)memset_s(admaDesc, ALIGN(host->admaDescSize, CACHE_ALIGNED_SIZE),
320 0, ALIGN(host->admaDescSize, CACHE_ALIGNED_SIZE));
322 for (i = 0; i < host->dmaSgCount; i++) {
323 addr = SDHCI_SG_DMA_ADDRESS(&host->sg[i]);
324 len = SDHCI_SG_DMA_LEN(&host->sg[i]);
333 SdhciSetAdmaDesc(host, admaDesc, addr, SDHCI_DMA_MAX_BUFF_SIZE, 0x21);
337 SdhciSetAdmaDesc(host, admaDesc, addr, len, 0x21);
340 admaDesc += host->admaDescLineSize;
343 if ((uint32_t)(admaDesc - host->admaDesc) > host->admaDescSize) {
348 if (host->quirks.bits.noEndattrInNopdesc) {
350 if (admaDesc != host->admaDesc) {
351 admaDesc -= host->admaDescLineSize;
355 SdhciSetAdmaDesc(host, admaDesc, 0, 0, 0x3);
357 SdhciDmaCacheClean((void*)VMM_TO_DMA_ADDR((uintptr_t)host->admaDesc),
358 ALIGN(host->admaDescSize, CACHE_ALIGNED_SIZE));
363 static void SdhciPrepareData(struct SdhciHost *host)
365 struct MmcCmd *cmd = host->cmd;
371 SdhciWriteb(host, SDHCI_DEFINE_TIMEOUT, TOUT_CTRL_R);
377 if (host->flags & (SDHCI_USE_ADMA | SDHCI_USE_SDMA)) {
378 host->flags |= SDHCI_REQ_USE_DMA;
381 if (host->flags & SDHCI_REQ_USE_DMA) {
382 if (host->flags & SDHCI_USE_ADMA) {
384 retval = SdhciAdmaTablePre(host, data);
386 host->flags &= ~SDHCI_REQ_USE_DMA;
388 SdhciWritel(host, 0, SDHCI_DMA_ADDRESS);
389 SdhciAdmaConfig(host);
393 SdhciWritel(host, SDHCI_SG_DMA_ADDRESS(&host->sg[0]), SDHCI_DMA_ADDRESS);
397 SdhciSetDmaConfig(host);
398 SdhciSetTransferIrqs(host);
399 SdhciSetBlkSizeReg(host, data->blockSize, SDHCI_DEFAULT_BOUNDARY_ARG);
400 SdhciWritew(host, data->blockNum, BLOCKCOUNT_R);
403 static void SdhciExecCmd(struct SdhciHost *host, struct MmcCmd *cmd)
417 /* wait host ready */
418 while (SdhciReadl(host, PSTATE_R) & mask) {
421 SdhciDumpregs(host);
423 SdhciTaskletFinish(host);
430 host->cmd = cmd;
431 SdhciPrepareData(host);
432 SdhciWritel(host, cmd->argument, ARGUMENT_R);
433 SdhciSetTransferMode(host, cmd);
436 HDF_LOGE("host%u: Unsupported response type!", host->hostId);
438 SdhciTaskletFinish(host);
443 SdhciWritew(host, SDHCI_GEN_CMD(cmd->cmdCode, flags), CMD_R);
448 struct SdhciHost *host = NULL;
458 host = (struct SdhciHost *)cntlr->priv;
459 if (host->quirks.bits.brokenCardDetection > 0 ||
460 host->quirks.bits.forceSWDetect > 0) {
463 return ((SdhciReadl(host, PSTATE_R) & SDHCI_CARD_PRESENT) > 0 ? true : false);
466 static int32_t SdhciFillDmaSg(struct SdhciHost *host)
468 struct MmcData *data = host->cmd->data;
477 host->sg = data->scatter;
478 host->dmaSgCount = data->scatterLen;
485 host->alignedBuff = (uint8_t *)OsalMemAllocAlign(CACHE_ALIGNED_SIZE, ALIGN(len, CACHE_ALIGNED_SIZE));
486 if (host->alignedBuff == NULL) {
491 ret = memcpy_s(host->alignedBuff, len, data->dataBuffer, len);
494 free(host->alignedBuff);
495 host->alignedBuff = NULL;
498 host->buffLen = len;
499 sg_init_one(&host->dmaSg, (const void *)host->alignedBuff, len);
500 host->dmaSgCount = 1;
501 host->sg = &host->dmaSg;
505 static void SdhciClearDmaSg(struct SdhciHost *host, struct MmcData *data)
514 if (host->alignedBuff != NULL && data->dataBuffer != NULL && len > 0 && host->buffLen > 0) {
516 (void)memcpy_s(data->dataBuffer, len, host->alignedBuff, host->buffLen);
519 if (host->alignedBuff != NULL) {
520 OsalMemFree(host->alignedBuff);
521 host->alignedBuff = NULL;
523 host->buffLen = 0;
524 host->dmaSgCount = 0;
525 host->sg = NULL;
528 static void SdhciDataSync(struct SdhciHost *host, struct MmcData *data)
533 for (i = 0; i < host->dmaSgCount; i++) {
534 sgLength = SDHCI_SG_DMA_LEN(&host->sg[i]);
535 sgPhyAddr = SDHCI_SG_DMA_ADDRESS(&host->sg[i]);
543 struct SdhciHost *host = (struct SdhciHost *)cntlr->priv;
548 (void)OsalMutexLock(&host->mutex);
550 host->cmd = cmd;
552 ret = SdhciFillDmaSg(host);
558 if (SdhciCardPlugged(host->mmc) == false || (host->flags & SDHCI_DEVICE_DEAD) > 0) {
561 SdhciEnableCardDetection(host);
565 SdhciExecCmd(host, cmd);
569 host->waitForEvent = true;
572 if (cmd->data == NULL && host->quirks.bits.forceSWDetect > 0) {
576 ret = SDHCI_EVENT_WAIT(&host->sdhciEvent, SDHCI_PEND_REQUEST_DONE | SDHCI_PEND_ACCIDENT, timeout);
579 host->waitForEvent = false;
583 SdhciDumpregs(host);
588 SdhciDoReset(host, SDHCI_RESET_CMD);
589 SdhciDoReset(host, SDHCI_RESET_DATA);
590 host->cmd = NULL;
592 SdhciDataSync(host, cmd->data);
596 SdhciClearDmaSg(host, cmd->data);
597 (void)OsalMutexUnlock(&host->mutex);
601 void SdhciResetDll(struct SdhciHost *host)
606 if (host->hostId >= SDHCI_MAX_HOST_NUM) {
610 reg = cfgArray[host->hostId];
616 static uint32_t SdhciSelectClock(struct SdhciHost *host, uint32_t clock)
622 if (host->hostId >= SDHCI_MAX_HOST_NUM) {
623 HDF_LOGE("host id=%u is not supported!", host->hostId);
627 if (host->hostId == 1 && (clock > SDHCI_MMC_FREQ_50M)) {
628 HDF_LOGE("host%u doesn't support freq %u!", host->hostId, clock);
658 reg = cfgArray[host->hostId];
683 static void SdhciEnableSample(struct SdhciHost *host)
687 val = SdhciReadl(host, AT_CTRL_R);
689 SdhciWritel(host, val, AT_CTRL_R);
692 static void SdhciSetSampPhase(struct SdhciHost *host, uint32_t phase)
695 val = SdhciReadl(host, AT_STAT_R);
696 val = SdhciReadl(host, AT_STAT_R);
699 SdhciWritel(host, val, AT_STAT_R);
717 static void SdhciSetSdiodriver(struct SdhciHost *host)
723 if (host->mmc->caps.bits.cap4Bit == 0) {
734 static void SdhciSetSdDriver(struct SdhciHost *host, enum MmcBusTiming timing)
740 if (host->mmc->caps.bits.cap4Bit == 0) {
763 static void SdhciSetEmmcCtrl(struct SdhciHost *host)
767 val = SdhciReadl(host, EMMC_CTRL_R);
769 SdhciWritel(host, val, EMMC_CTRL_R);
772 static void SdhciSetEmmcDriver(struct SdhciHost *host, enum MmcBusTiming timing)
780 SdhciSetEmmcCtrl(host);
790 SdhciSetEmmcCtrl(host);
799 SdhciSetEmmcCtrl(host);
818 static void SdhciSetMmcIoDriver(struct SdhciHost *host, enum MmcBusTiming timing)
822 if (host->hostId == 0) {
826 SdhciSetEmmcDriver(host, timing);
830 SdhciSetSdDriver(host, timing);
832 } else if (host->hostId == 1) {
834 SdhciSetSdiodriver(host);
838 static void SdhciSetPhase(struct SdhciHost *host)
843 if (host->mmc->curDev == NULL) {
846 timing = host->mmc->curDev->workPara.timing;
848 if (host->hostId == 0) {
852 phase = host->tuningPhase;
855 phase = host->tuningPhase;
882 SdhciSetDrvPhase(host->hostId, drvPhase);
883 SdhciEnableSample(host);
884 SdhciSetSampPhase(host, phase);
885 SdhciSetMmcIoDriver(host, timing);
890 struct SdhciHost *host = (struct SdhciHost *)cntlr->priv;
895 clk = SdhciReadw(host, CLK_CTRL_R);
897 SdhciWritew(host, clk, CLK_CTRL_R);
902 SdhciWritew(host, clk, CLK_CTRL_R);
907 if (clock >= host->maxClk) {
908 clock = host->maxClk;
911 SdhciResetDll(host);
912 SdhciSetPhase(host);
914 ret = SdhciSelectClock(host, clock);
919 host->clock = ret;
921 SdhciResetDll(host);
926 SdhciWritew(host, clk, CLK_CTRL_R);
928 clk = SdhciReadw(host, CLK_CTRL_R);
939 SdhciResetDll(host);
942 SdhciWritew(host, clk, CLK_CTRL_R);
946 static void SdhciInit(struct SdhciHost *host, bool resetAll)
950 SdhciDoReset(host, (SDHCI_RESET_CMD | SDHCI_RESET_DATA));
952 SdhciDoReset(host, SDHCI_RESET_ALL);
955 host->pwr = 0;
956 host->irqEnable = SDHCI_INTERRUPT_BUS_POWER | SDHCI_INTERRUPT_DATA_END_BIT | SDHCI_INTERRUPT_DATA_CRC |
961 SdhciEnablePlugIrq(host, host->irqEnable);
964 host->clock = 0;
966 reg = SdhciReadw(host, MSHC_CTRL_R);
968 SdhciWritew(host, reg, MSHC_CTRL_R);
970 reg = SdhciReadl(host, MBIU_CTRL_R);
973 SdhciWritel(host, reg, MBIU_CTRL_R);
975 reg = SdhciReadl(host, MULTI_CYCLE_R);
978 SdhciWritel(host, reg, MULTI_CYCLE_R);
982 static void SdhciReinit(struct SdhciHost *host)
984 SdhciInit(host, true);
986 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
987 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
988 host->mmc->maxBlkNum = SDHCI_MAX_BLK_NUM;
990 SdhciEnableCardDetection(host);
993 static void SdhciEnablePresetValue(struct SdhciHost *host, bool enable)
997 if (host->version < SDHCI_HOST_SPEC_300) {
1001 if (host->presetEnabled != enable) {
1002 reg = SdhciReadw(host, HOST_CTRL2_R);
1008 SdhciWritew(host, reg, HOST_CTRL2_R);
1011 host->flags |= SDHCI_PV_ENABLED;
1013 host->flags &= ~SDHCI_PV_ENABLED;
1015 host->presetEnabled = enable;
1021 struct SdhciHost *host = (struct SdhciHost *)cntlr->priv;
1025 SdhciWritel(host, 0, NORMAL_INT_SIGNAL_EN_R);
1026 SdhciReinit(host);
1028 if (host->version >= SDHCI_HOST_SPEC_300) {
1029 SdhciEnablePresetValue(host, false);
1031 if (host->pwr == SDHCI_POWER_330) {
1035 host->pwr = pwr;
1037 SdhciWriteb(host, 0, PWR_CTRL_R);
1038 SdhciWriteb(host, pwr, PWR_CTRL_R);
1040 SdhciWriteb(host, pwr, PWR_CTRL_R);
1048 struct SdhciHost *host = (struct SdhciHost *)cntlr->priv;
1051 val = SdhciReadb(host, HOST_CTRL1_R);
1054 if (host->version >= SDHCI_HOST_SPEC_300) {
1058 if (host->version >= SDHCI_HOST_SPEC_300) {
1067 SdhciWriteb(host, val, HOST_CTRL1_R);
1071 static void SdhciSetUhsSignaling(struct SdhciHost *host, enum MmcBusTiming timing)
1075 val = SdhciReadw(host, HOST_CTRL2_R);
1077 /* Select Bus Speed Mode for host */
1092 SdhciWritew(host, val, HOST_CTRL2_R);
1097 struct SdhciHost *host = (struct SdhciHost *)cntlr->priv;
1100 ctrl1Val = SdhciReadb(host, HOST_CTRL1_R);
1106 if (host->version < SDHCI_HOST_SPEC_300) {
1107 SdhciWriteb(host, ctrl1Val, HOST_CTRL1_R);
1111 if (host->presetEnabled == false) {
1112 SdhciWriteb(host, ctrl1Val, HOST_CTRL1_R);
1113 ctrl2Val = SdhciReadw(host, HOST_CTRL2_R);
1116 SdhciWritew(host, ctrl2Val, HOST_CTRL2_R);
1118 clockVal = SdhciReadw(host, CLK_CTRL_R);
1120 SdhciWritew(host, clockVal, CLK_CTRL_R);
1122 SdhciWriteb(host, ctrl1Val, HOST_CTRL1_R);
1123 (void)SdhciSetClock(cntlr, host->clock);
1125 clockVal = SdhciReadw(host, CLK_CTRL_R);
1127 SdhciWritew(host, clockVal, CLK_CTRL_R);
1129 SdhciSetUhsSignaling(host, timing);
1131 SdhciEnablePresetValue(host, true);
1133 (void)SdhciSetClock(cntlr, host->clock);
1139 struct SdhciHost *host = (struct SdhciHost *)cntlr->priv;
1142 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1144 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1147 if ((host->flags & SDHCI_DEVICE_DEAD) == 0) {
1149 host->irqEnable |= SDHCI_INTERRUPT_CARD_INT;
1151 host->irqEnable &= ~SDHCI_INTERRUPT_CARD_INT;
1153 SdhciEnablePlugIrq(host, host->irqEnable);
1160 struct SdhciHost *host = (struct SdhciHost *)cntlr->priv;
1162 SdhciWritel(host, 0x0, EMMC_HW_RESET_R);
1164 SdhciWritel(host, 0x1, EMMC_HW_RESET_R);
1172 struct SdhciHost *host = NULL;
1178 host = (struct SdhciHost *)cntlr->priv;
1179 SdhciInit(host, true);
1180 SdhciEnableCardDetection(host);
1186 struct SdhciHost *host = (struct SdhciHost *)cntlr->priv;
1189 reg = SdhciReadl(host, EMMC_CTRL_R);
1195 SdhciWritel(host, reg, EMMC_CTRL_R);
1197 reg = SdhciReadl(host, MULTI_CYCLE_R);
1203 SdhciWritel(host, reg, MULTI_CYCLE_R);
1210 struct SdhciHost *host = (struct SdhciHost *)cntlr->priv;
1213 ctrl = SdhciReadw(host, HOST_CTRL2_R);
1216 SdhciWritew(host, ctrl, HOST_CTRL2_R);
1219 SdhciWritew(host, ctrl, HOST_CTRL2_R);
1234 struct SdhciHost *host = (struct SdhciHost *)cntlr->priv;
1236 if (host->flags & SDHCI_DEVICE_DEAD) {
1239 val = SdhciReadl(host, PSTATE_R);
1243 if (host->quirks.bits.invertedWriteProtect > 0) {
1251 struct SdhciHost *host = (struct SdhciHost *)cntlr->priv;
1255 state = SdhciReadl(host, PSTATE_R);
1275 HDF_LOGD("host%u: DRV DLL not locked.", id);
1292 static void SdhciPreTune(struct SdhciHost *host)
1296 val = SdhciReadl(host, NORMAL_INT_STAT_EN_R);
1298 SdhciWritel(host, val, NORMAL_INT_STAT_EN_R);
1300 val = SdhciReadl(host, NORMAL_INT_SIGNAL_EN_R);
1302 SdhciWritel(host, val, NORMAL_INT_SIGNAL_EN_R);
1304 SdhciWaitDrvDllLock(host->hostId);
1305 SdhciEnableSamplDll(host->hostId);
1306 SdhciEnableSample(host);
1309 static void SdhciEnableEdgeTune(struct SdhciHost *host)
1314 if (host->hostId >= (sizeof(offset) / sizeof(offset[0]))) {
1317 val = OSAL_READL(offset[host->hostId]);
1319 OSAL_WRITEL(val, offset[host->hostId]);
1320 val = SdhciReadl(host, MULTI_CYCLE_R);
1323 SdhciWritel(host, val, MULTI_CYCLE_R);
1342 HDF_LOGD("host%u: SAMPL DLL not ready.", id);
1345 static void SdhciCardClk(struct SdhciHost *host, bool action)
1349 value = SdhciReadl(host, CLK_CTRL_R);
1357 SdhciWritel(host, value, CLK_CTRL_R);
1360 static void SdhciSelectSamplPhase(struct SdhciHost *host, uint32_t phase)
1362 SdhciCardClk(host, false);
1363 SdhciSetSampPhase(host, phase);
1364 SdhciWaitSamplDllReady(host->hostId);
1365 SdhciCardClk(host, true);
1369 static void SdhciDisEdgeTune(struct SdhciHost *host)
1373 val = SdhciReadl(host, MULTI_CYCLE_R);
1375 SdhciWritel(host, val, MULTI_CYCLE_R);
1378 static void SdhciPostTune(struct SdhciHost *host)
1383 ctrl = SdhciReadw(host, HOST_CTRL2_R);
1385 SdhciWritew(host, ctrl, HOST_CTRL2_R);
1387 val = SdhciReadl(host, NORMAL_INT_STAT_EN_R);
1389 SdhciWritel(host, val, NORMAL_INT_STAT_EN_R);
1390 val = SdhciReadl(host, NORMAL_INT_SIGNAL_EN_R);
1392 SdhciWritel(host, val, NORMAL_INT_SIGNAL_EN_R);
1395 static void SdhciDoTune(struct SdhciHost *host, uint32_t opcode, uint32_t start, uint32_t end)
1405 SdhciSelectSamplPhase(host, index % SDHCI_PHASE_SCALE);
1406 err = MmcSendTuning(host->mmc, opcode, true);
1433 host->tuningPhase = phase;
1434 SdhciSelectSamplPhase(host, phase);
1435 SdhciPostTune(host);
1440 struct SdhciHost *host = (struct SdhciHost *)cntlr->priv;
1450 SdhciPreTune(host);
1451 SdhciEnableEdgeTune(host);
1453 SdhciSelectSamplPhase(host, index * SDHCI_PHASE_SCALE_TIMES);
1456 val = SdhciReadl(host, MULTI_CYCLE_R);
1475 HDF_LOGE("host%u: tuning failed! can not found edge!", host->hostId);
1478 SdhciDisEdgeTune(host);
1486 SdhciDoTune(host, cmdCode, start, end);
1492 struct SdhciHost *host = NULL;
1498 host = (struct SdhciHost *)cntlr->priv;
1499 if (host->waitForEvent == true) {
1500 (void)SDHCI_EVENT_SIGNAL(&host->sdhciEvent, SDHCI_PEND_ACCIDENT);
1524 static void SdhciDeleteHost(struct SdhciHost *host)
1528 if (host == NULL) {
1532 cntlr = host->mmc;
1544 host->mmc = NULL;
1547 OsalUnregisterIrq(host->irqNum, host);
1548 if (host->admaDesc != NULL) {
1549 OsalMemFree(host->admaDesc);
1550 host->admaDesc = NULL;
1552 if (host->base != NULL) {
1553 OsalIoUnmap(host->base);
1556 (void)SDHCI_EVENT_DELETE(&host->sdhciEvent);
1557 (void)OsalMutexDestroy(&host->mutex);
1558 OsalMemFree(host);
1561 static int32_t SdhciHostParse(struct SdhciHost *host, struct HdfDeviceObject *obj)
1568 if (obj == NULL || host == NULL) {
1594 host->base = OsalIoRemap(regBase, regSize);
1595 if (host->base == NULL) {
1600 ret = drsOps->GetUint32(node, "irqNum", &(host->irqNum), 0);
1605 ret = drsOps->GetUint32(node, "quirks", &(host->quirks.quirksData), 0);
1608 host->quirks.quirksData = 0;
1613 static void SdhciCrgInit(struct SdhciHost *host)
1617 if (host->hostId >= SDHCI_MAX_HOST_NUM) {
1622 reg = cfgArray[host->hostId];
1628 reg = cfgArray[host->hostId];
1637 /* reset of host contorl is done */
1644 SdhciCardClk(host, false);
1646 if (host->mmc->devType == MMC_DEV_EMMC) {
1647 (void)SdhciSelectClock(host, SDHCI_MMC_FREQ_150M);
1649 (void)SdhciSelectClock(host, SDHCI_MMC_FREQ_50M);
1653 SdhciSetDrvPhase(host->hostId, 0x10);
1658 SdhciCardClk(host, true);
1661 value = SdhciReadl(host, CLK_CTRL_R);
1663 SdhciWritel(host, value, CLK_CTRL_R);
1668 static void SdhciUpdateCapFlag(struct SdhciHost *host, uint32_t cap)
1670 struct MmcCntlr *mmc = host->mmc;
1673 host->flags |= SDHCI_USE_SDMA;
1676 if ((host->version >= SDHCI_HOST_SPEC_200) && (cap & SDHCI_SUPPORT_ADMA2)) {
1677 host->flags |= SDHCI_USE_ADMA;
1679 host->flags |= SDHCI_USE_64BIT_ADMA;
1683 if ((host->version >= SDHCI_HOST_SPEC_300 && (host->flags & SDHCI_USE_ADMA) > 0) ||
1684 (host->flags & SDHCI_USE_SDMA) == 0) {
1685 host->flags |= SDHCI_AUTO_CMD23;
1689 host->flags |= SDHCI_HOST_IRQ_STATUS;
1691 host->flags &= ~(SDHCI_SUPPORT_SDMA | SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12);
1693 host->flags &= ~(SDHCI_SUPPORT_SDMA);
1694 host->flags |= SDHCI_AUTO_CMD23;
1698 static int32_t SdhciFillAdmaInfo(struct SdhciHost *host)
1700 if (host->flags & SDHCI_USE_ADMA) {
1701 host->admaMaxDesc = SDHCI_ADMA_MAX_DESC;
1702 host->admaDescSize = SDHCI_ADMA_DEF_SIZE;
1704 if (host->flags & SDHCI_USE_64BIT_ADMA) {
1705 host->admaDescLineSize = SDHCI_ADMA_64BIT_LINE_SIZE;
1707 host->admaDescLineSize = SDHCI_ADMA_LINE_SIZE;
1709 host->admaDescSize = (host->admaMaxDesc * 2 + 1) * host->admaDescLineSize;
1710 host->admaDesc = (void *)OsalMemAllocAlign(CACHE_ALIGNED_SIZE, ALIGN(host->admaDescSize, CACHE_ALIGNED_SIZE));
1711 if (host->admaDesc == NULL) {
1722 static void SdhciFillClkInfo(struct SdhciHost *host, uint32_t cap1, uint32_t cap2)
1724 struct MmcCntlr *mmc = host->mmc;
1726 if (host->version >= SDHCI_HOST_SPEC_300) {
1727 host->maxClk = (cap1 & SDHCI_BASIC_FREQ_OF_CLK_MASK) >> SDHCI_BASIC_FREQ_OF_CLK_SHIFT;
1729 host->maxClk = (cap1 & SDHCI_CLK_BASE_MASK) >> SDHCI_BASIC_FREQ_OF_CLK_SHIFT;
1732 host->maxClk *= 1000000;
1733 host->clkMul = (cap2 & SDHCI_CLK_MUL_MASK) >> SDHCI_CLK_MUL_SHIFT;
1735 if (host->clkMul) {
1736 host->clkMul += 1;
1739 mmc->freqMax = host->maxClk;
1741 host->maxClk = mmc->freqMax;
1745 if (host->version >= SDHCI_HOST_SPEC_300) {
1746 if (host->clkMul) {
1747 mmc->freqMin = (host->maxClk * host->clkMul) / 1024;
1748 mmc->freqMax = host->maxClk * host->clkMul;
1750 mmc->freqMin = host->maxClk / SDHCI_MAX_DIV_SPEC_300;
1753 mmc->freqMin = host->maxClk / SDHCI_MAX_DIV_SPEC_200;
1758 static void SdhciUpdateDrvCap(struct SdhciHost *host, uint32_t cap1, uint32_t cap2)
1760 struct MmcCntlr *mmc = host->mmc;
1783 if (host->flags & SDHCI_USE_ADMA) {
1784 mmc->maxReqSize = host->admaMaxDesc * 65536;
1792 static void SdhciEnableSdioIrqNoLock(struct SdhciHost *host, bool enable)
1794 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1796 host->irqEnable |= SDHCI_INTERRUPT_CARD_INT;
1798 host->irqEnable &= ~SDHCI_INTERRUPT_CARD_INT;
1800 SdhciEnablePlugIrq(host, host->irqEnable);
1804 static void SdhciSaveCommandResp(struct SdhciHost *host, struct MmcCmd *cmd)
1809 cmd->resp[i] = SdhciReadl(host, RESP01_R + (3 - i) * 4) << 8;
1811 cmd->resp[i] |= SdhciReadb(host, RESP01_R + (3 - i) * 4 - 1);
1816 static void SdhciFinishCommand(struct SdhciHost *host)
1818 struct MmcCmd *cmd = host->cmd;
1826 SdhciSaveCommandResp(host, cmd);
1828 cmd->resp[0] = SdhciReadl(host, RESP01_R);
1833 SdhciTaskletFinish(host);
1837 static void SdhciCmdIrq(struct SdhciHost *host, uint32_t intMask)
1839 if (host->cmd == NULL) {
1844 host->cmd->returnError = HDF_ERR_TIMEOUT;
1846 host->cmd->returnError = HDF_MMC_ERR_ILLEGAL_SEQ;
1849 if (host->cmd->data == NULL && host->cmd->returnError != HDF_SUCCESS) {
1850 SdhciTaskletFinish(host);
1854 if (host->cmd->respType & RESP_BUSY) {
1859 SdhciFinishCommand(host);
1863 static void SdhciFinishData(struct SdhciHost *host)
1865 struct MmcData *data = host->cmd->data;
1869 SdhciDoReset(host, SDHCI_RESET_CMD);
1870 SdhciDoReset(host, SDHCI_RESET_DATA);
1872 SdhciExecCmd(host, &(data->stopCmd));
1874 SdhciTaskletFinish(host);
1878 static void SdhciDataIrq(struct SdhciHost *host, uint32_t intMask)
1881 struct MmcCmd *cmd = host->cmd;
1887 SdhciTaskletFinish(host);
1891 SdhciFinishCommand(host);
1911 command = SDHCI_PARSE_CMD(SdhciReadw(host, CMD_R));
1914 SdhciDumpregs(host);
1916 SdhciFinishData(host);
1919 SdhciFinishData(host);
1928 struct SdhciHost *host = (struct SdhciHost *)data;
1932 if (host == NULL || host->mmc == NULL) {
1937 while ((intMask = SdhciReadl(host, NORMAL_INT_STAT_R)) != 0) {
1938 SdhciWritel(host, intMask, NORMAL_INT_STAT_R);
1940 host->irqEnable &= ~SDHCI_CART_PLUG_STATE;
1941 host->irqEnable |= SDHCI_PLUG_STATE(host) ? SDHCI_INTERRUPT_CARD_REMOVE : SDHCI_INTERRUPT_CARD_INSERT;
1942 SdhciEnablePlugIrq(host, host->irqEnable);
1943 SdhciWritel(host, intMask & SDHCI_CART_PLUG_STATE, NORMAL_INT_STAT_R);
1944 MmcCntlrAddPlugMsgToQueue(host->mmc);
1945 if (host->waitForEvent) {
1946 (void)SDHCI_EVENT_SIGNAL(&host->sdhciEvent, SDHCI_PEND_ACCIDENT);
1951 SdhciCmdIrq(host, (intMask & SDHCI_INT_CMD_MASK));
1954 SdhciDataIrq(host, (intMask & SDHCI_INT_DATA_MASK));
1957 HDF_LOGD("host%u: card is consuming too much power!", host->hostId);
1960 SdhciEnableSdioIrqNoLock(host, false);
1961 MmcCntlrNotifySdioIrqThread(host->mmc);
1967 static int32_t SdhciHostInit(struct SdhciHost *host, struct MmcCntlr *cntlr)
1973 host->hostId = (uint32_t)cntlr->index;
1974 if (SDHCI_EVENT_INIT(&host->sdhciEvent) != HDF_SUCCESS) {
1978 if (OsalMutexInit(&host->mutex) != HDF_SUCCESS) {
1983 SdhciCrgInit(host);
1984 host->version = SdhciReadw(host, HOST_VERSION_R);
1985 host->version = (host->version & SDHCI_HOST_SPEC_VER_MASK);
1986 Capability1 = SdhciReadl(host, CAPABILITIES1_R);
1987 if (host->version >= SDHCI_HOST_SPEC_300) {
1988 Capability2 = SdhciReadl(host, CAPABILITIES2_R);
1991 SdhciUpdateCapFlag(host, Capability1);
1992 ret = SdhciFillAdmaInfo(host);
1999 SdhciFillClkInfo(host, Capability1, Capability2);
2000 SdhciUpdateDrvCap(host, Capability1, Capability2);
2001 ret = SdhciSystemInit(host->mmc);
2006 ret = OsalRegisterIrq(host->irqNum, 0, (OsalIRQHandle)SdhciIrqHandler, "MMC_IRQ", host);
2017 struct SdhciHost *host = NULL;
2029 host = (struct SdhciHost *)OsalMemCalloc(sizeof(struct SdhciHost));
2030 if (host == NULL) {
2036 host->mmc = cntlr;
2037 cntlr->priv = (void *)host;
2046 ret = SdhciHostParse(host, obj);
2050 ret = SdhciHostInit(host, cntlr);
2063 SdhciDeleteHost(host);