Lines Matching refs:SdhciWritel
98 SdhciWritel(host, irq, NORMAL_INT_STAT_EN_R);
99 SdhciWritel(host, irq, NORMAL_INT_SIGNAL_EN_R);
123 SdhciWritel(host, host->irqEnable, NORMAL_INT_STAT_EN_R);
124 SdhciWritel(host, host->irqEnable, NORMAL_INT_SIGNAL_EN_R);
175 SdhciWritel(host, cmd->data->blockNum, SDHCI_ARGUMENT2);
272 SdhciWritel(host, SDHCI_MAKE_BLKSZ(7, blksz), BLOCKSIZE_R);
274 SdhciWritel(host, SDHCI_MAKE_BLKSZ(sdmaBoundary, blksz), BLOCKSIZE_R);
280 SdhciWritel(host, 0, (uintptr_t)ADMA_SA_HIGH_R);
281 SdhciWritel(host, VMM_TO_DMA_ADDR((uintptr_t)host->admaDesc), (uintptr_t)ADMA_SA_LOW_R);
388 SdhciWritel(host, 0, SDHCI_DMA_ADDRESS);
393 SdhciWritel(host, SDHCI_SG_DMA_ADDRESS(&host->sg[0]), SDHCI_DMA_ADDRESS);
432 SdhciWritel(host, cmd->argument, ARGUMENT_R);
689 SdhciWritel(host, val, AT_CTRL_R);
699 SdhciWritel(host, val, AT_STAT_R);
769 SdhciWritel(host, val, EMMC_CTRL_R);
973 SdhciWritel(host, reg, MBIU_CTRL_R);
978 SdhciWritel(host, reg, MULTI_CYCLE_R);
1025 SdhciWritel(host, 0, NORMAL_INT_SIGNAL_EN_R);
1162 SdhciWritel(host, 0x0, EMMC_HW_RESET_R);
1164 SdhciWritel(host, 0x1, EMMC_HW_RESET_R);
1195 SdhciWritel(host, reg, EMMC_CTRL_R);
1203 SdhciWritel(host, reg, MULTI_CYCLE_R);
1298 SdhciWritel(host, val, NORMAL_INT_STAT_EN_R);
1302 SdhciWritel(host, val, NORMAL_INT_SIGNAL_EN_R);
1323 SdhciWritel(host, val, MULTI_CYCLE_R);
1357 SdhciWritel(host, value, CLK_CTRL_R);
1375 SdhciWritel(host, val, MULTI_CYCLE_R);
1389 SdhciWritel(host, val, NORMAL_INT_STAT_EN_R);
1392 SdhciWritel(host, val, NORMAL_INT_SIGNAL_EN_R);
1663 SdhciWritel(host, value, CLK_CTRL_R);
1938 SdhciWritel(host, intMask, NORMAL_INT_STAT_R);
1943 SdhciWritel(host, intMask & SDHCI_CART_PLUG_STATE, NORMAL_INT_STAT_R);