Lines Matching refs:val
33 static inline int32_t FephyExpandedWrite(struct HiethNetdevLocal *ld, int32_t phyAddr, int32_t regNum, int32_t val)
36 return HiethMdioWrite(ld, phyAddr, MII_EXPMD, val);
41 uint16_t val;
46 val = FephyExpandedRead(ld, phyAccess->phyAddr, REG_DEF_ATE);
47 val &= BIT_AUTOTRIM_DONE; /* (0x1 << 0) */
48 } while (!val && --timeout);
58 uint32_t val;
62 val = readl(SYS_CTRL_REG_BASE + 0x8024);
63 ldSet = (val >> BIT_OFFSET_LD_SET) & BIT_MASK_LD_SET;
64 ldoSet = (val >> BIT_OFFSET_LDO_SET) & BIT_MASK_LDO_SET;
65 tuning = (val >> BIT_OFFSET_R_TUNING) & BIT_MASK_R_TUNING;
70 val = FephyExpandedRead(ld, phyAccess->phyAddr, REG_LD_AM);
71 val = (val & ~BIT_MASK_LD_SET) | (ldSet & BIT_MASK_LD_SET);
72 FephyExpandedWrite(ld, phyAccess->phyAddr, REG_LD_AM, val);
74 val = FephyExpandedRead(ld, phyAccess->phyAddr, REG_LDO_AM);
75 val = (val & ~BIT_MASK_LDO_SET) | (ldoSet & BIT_MASK_LDO_SET);
76 FephyExpandedWrite(ld, phyAccess->phyAddr, REG_LDO_AM, val);
78 val = FephyExpandedRead(ld, phyAccess->phyAddr, REG_R_TUNING);
79 val = (val & ~BIT_MASK_R_TUNING) | (tuning & BIT_MASK_R_TUNING);
80 FephyExpandedWrite(ld, phyAccess->phyAddr, REG_R_TUNING, val);
82 val = FephyExpandedRead(ld, phyAccess->phyAddr, REG_WR_DONE);
83 if (val & BIT_CFG_ACK) {
86 val = val | BIT_CFG_DONE;
88 FephyExpandedWrite(ld, phyAccess->phyAddr, REG_WR_DONE, val);
92 val = FephyExpandedRead(ld, phyAccess->phyAddr, REG_WR_DONE);
93 val &= BIT_CFG_ACK;
94 } while (!val && --timeout);
131 uint32_t val;
133 READ_UINT32(val, HIETH_CRG_IOBASE);
134 val |= ETH_PHY_RESET;
135 WRITE_UINT32(val, HIETH_CRG_IOBASE);
139 READ_UINT32(val, HIETH_CRG_IOBASE);
140 val &= ~ETH_PHY_RESET;
141 WRITE_UINT32(val, HIETH_CRG_IOBASE);
351 txqCur->tx.val = 0;
368 HwXmitqPkg(ld, VMM_TO_DMA_ADDR(txqCur->txAddr), txqCur->tx.val);