Lines Matching defs:ld
27 static inline int32_t FephyExpandedRead(struct HiethNetdevLocal *ld, int32_t phyAddr, int32_t regNum)
29 HiethMdioWrite(ld, phyAddr, MII_EXPMA, regNum);
30 return HiethMdioRead(ld, phyAddr, MII_EXPMD);
33 static inline int32_t FephyExpandedWrite(struct HiethNetdevLocal *ld, int32_t phyAddr, int32_t regNum, int32_t val)
35 HiethMdioWrite(ld, phyAddr, MII_EXPMA, regNum);
36 return HiethMdioWrite(ld, phyAddr, MII_EXPMD, val);
39 static void HiethFephyUseDefaultTrim(struct HiethNetdevLocal *ld, const EthPhyAccess *phyAccess)
46 val = FephyExpandedRead(ld, phyAccess->phyAddr, REG_DEF_ATE);
56 void HiethFephyTrim(struct HiethNetdevLocal *ld, const EthPhyAccess *phyAccess)
67 HiethFephyUseDefaultTrim(ld, phyAccess);
70 val = FephyExpandedRead(ld, phyAccess->phyAddr, REG_LD_AM);
72 FephyExpandedWrite(ld, phyAccess->phyAddr, REG_LD_AM, val);
74 val = FephyExpandedRead(ld, phyAccess->phyAddr, REG_LDO_AM);
76 FephyExpandedWrite(ld, phyAccess->phyAddr, REG_LDO_AM, val);
78 val = FephyExpandedRead(ld, phyAccess->phyAddr, REG_R_TUNING);
80 FephyExpandedWrite(ld, phyAccess->phyAddr, REG_R_TUNING, val);
82 val = FephyExpandedRead(ld, phyAccess->phyAddr, REG_WR_DONE);
88 FephyExpandedWrite(ld, phyAccess->phyAddr, REG_WR_DONE, val);
92 val = FephyExpandedRead(ld, phyAccess->phyAddr, REG_WR_DONE);
103 static inline void HiethEnableRxcsumDrop(struct HiethNetdevLocal *ld, bool drop)
105 HiethWritelBits(ld, drop, UD_REG_NAME(GLB_RX_COE_CTRL), BITS_COE_IPHDR_DROP);
106 HiethWritelBits(ld, false, UD_REG_NAME(GLB_RX_COE_CTRL), BITS_COE_PAYLOAD_DROP);
107 HiethWritelBits(ld, drop, UD_REG_NAME(GLB_RX_COE_CTRL), BITS_COE_IPV6_UDP_ZERO_DROP);
110 void HiethHwMacCoreInit(struct HiethNetdevLocal *ld)
112 OsalSpinInit(&(ld->tx_lock));
113 OsalSpinInit(&(ld->rx_lock));
116 HiethEnableRxcsumDrop(ld, true);
120 ld->sgHead = ld->sgTail = 0;
121 ld->txqHead = ld->txqTail = 0;
123 ld->txHwCnt = 0;
126 (void)HiethSetHwqDepth(ld);
146 static inline int32_t IrqEnable(struct HiethNetdevLocal *ld, int32_t irqs)
150 old = HiethRead(ld, GLB_RW_IRQ_ENA);
151 HiethWrite(ld, old | (unsigned long)irqs, GLB_RW_IRQ_ENA);
152 old = HiethRead(ld, GLB_RW_IRQ_ENA);
156 static inline int32_t IrqDisable(struct HiethNetdevLocal *ld, int32_t irqs)
160 old = HiethRead(ld, GLB_RW_IRQ_ENA);
161 HiethWrite(ld, old & (~(unsigned long)irqs), GLB_RW_IRQ_ENA);
165 static inline int32_t ReadIrqstatus(struct HiethNetdevLocal *ld)
169 status = HiethRead(ld, GLB_RO_IRQ_STAT);
173 int32_t HiethHwSetMacAddress(struct HiethNetdevLocal *ld, int32_t ena, const uint8_t *mac)
177 if (ld->port == DOWN_PORT) {
178 HiethWritelBits(ld, 1, GLB_DN_HOSTMAC_ENA, BITS_DN_HOST_ENA);
182 if (ld->port == UP_PORT) {
183 HiethWrite(ld, reg, GLB_HOSTMAC_H16);
185 HiethWrite(ld, reg, GLB_DN_HOSTMAC_H16);
189 if (ld->port == UP_PORT) {
190 HiethWrite(ld, reg, GLB_HOSTMAC_L32);
192 HiethWrite(ld, reg, GLB_DN_HOSTMAC_L32);
197 int32_t HiethHwGetMacAddress(struct HiethNetdevLocal *ld, uint8_t *mac)
201 if (ld->port == UP_PORT) {
202 reg = HiethRead(ld, GLB_HOSTMAC_H16);
204 reg = HiethRead(ld, GLB_DN_HOSTMAC_H16);
209 if (ld->port == UP_PORT) {
210 reg = HiethRead(ld, GLB_HOSTMAC_L32);
212 reg = HiethRead(ld, GLB_DN_HOSTMAC_L32);
221 int32_t TestXmitQueueReady(struct HiethNetdevLocal *ld)
223 return HiethReadlBits(ld, UD_REG_NAME(GLB_RO_QUEUE_STAT), BITS_XMITQ_RDY);
226 int32_t HiethIrqEnable(struct HiethNetdevLocal *ld, int32_t irqs)
231 old = IrqEnable(ld, irqs);
236 int32_t HiethIrqDisable(struct HiethNetdevLocal *ld, int32_t irqs)
241 old = IrqDisable(ld, irqs);
246 int32_t HiethReadIrqstatus(struct HiethNetdevLocal *ld)
248 return ReadIrqstatus(ld);
251 int32_t HiethClearIrqstatus(struct HiethNetdevLocal *ld, int32_t irqs)
256 HiethWrite(ld, irqs, GLB_RW_IRQ_RAW);
257 status = ReadIrqstatus(ld);
262 int32_t HiethSetEndianMode(struct HiethNetdevLocal *ld, int32_t mode)
266 old = HiethReadlBits(ld, GLB_ENDIAN_MOD, BITS_ENDIAN);
267 HiethWritelBits(ld, mode, GLB_ENDIAN_MOD, BITS_ENDIAN);
271 int32_t HiethSetHwqDepth(struct HiethNetdevLocal *ld)
273 HiethAssert(ld->depth.hwXmitq > 0 && ld->depth.hwXmitq <= HIETH_MAX_QUEUE_DEPTH);
274 if ((ld->depth.hwXmitq) > HIETH_MAX_QUEUE_DEPTH) {
278 HiethWritelBits(ld, ld->depth.hwXmitq, UD_REG_NAME(GLB_QLEN_SET), BITS_TXQ_DEP);
279 HiethWritelBits(ld, HIETH_MAX_QUEUE_DEPTH - ld->depth.hwXmitq, UD_REG_NAME(GLB_QLEN_SET), BITS_RXQ_DEP);
283 int32_t HiethXmitReleasePkt(struct HiethNetdevLocal *ld, const HiethPriv *priv)
290 OsalSpinLockIrq(&(ld->tx_lock));
292 while (HwXmitqCntInUse(ld) < ld->txHwCnt) {
293 HiethAssert(ld->txHwCnt);
295 txqCur = ld->txq + ld->txqTail;
299 pbuf = priv->ram->pbufInfo + ld->txqTail;
308 ld->txqTail++;
309 if (ld->txqTail == ld->qSize) {
310 ld->txqTail = 0;
314 ld->txHwCnt--;
317 if (txReclaimCnt && ld->txBusy) {
318 ld->txBusy = 0;
323 OsalSpinUnlockIrq(&(ld->tx_lock));
327 int32_t HiethXmitGso(struct HiethNetdevLocal *ld, const HiethPriv *priv, NetBuf *netBuf)
343 pbInfo = &(priv->ram->pbufInfo[ld->txqHead]);
350 txqCur = ld->txq + ld->txqHead;
368 HwXmitqPkg(ld, VMM_TO_DMA_ADDR(txqCur->txAddr), txqCur->tx.val);
369 ld->txqHead++;
370 if (ld->txqHead == ld->qSize) {
371 ld->txqHead = 0;
376 int32_t HiethFeedHw(struct HiethNetdevLocal *ld, HiethPriv *priv)
382 OsalSpinLockIrq(&(ld->rx_lock));
384 while (HiethReadlBits(ld, UD_REG_NAME(GLB_RO_QUEUE_STAT), BITS_RECVQ_RDY)) {
411 HiethWrite(ld, VMM_TO_DMA_ADDR((UINTPTR)NetBufGetAddress(netBuf, E_DATA_BUF)), UD_REG_NAME(GLB_IQ_ADDR));
416 OsalSpinUnlockIrq(&(ld->rx_lock));