Lines Matching refs:desc
184 /* always use desc[0] [1] ([2]) for request-wait-response */
211 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)req));
212 q->desc[idx].len = reqSize;
213 q->desc[idx].flag = VIRTQ_DESC_F_NEXT;
214 q->desc[idx].next = idx + 1;
216 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)resp));
217 q->desc[idx].len = respSize;
218 q->desc[idx].flag = VIRTQ_DESC_F_WRITE;
229 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)req));
230 q->desc[idx].len = reqSize;
231 q->desc[idx].flag = VIRTQ_DESC_F_NEXT;
232 q->desc[idx].next = idx + 1;
234 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)data));
235 q->desc[idx].len = dataSize;
236 q->desc[idx].flag = VIRTQ_DESC_F_NEXT;
237 q->desc[idx].next = idx + 1;
239 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)resp));
240 q->desc[idx].len = respSize;
241 q->desc[idx].flag = VIRTQ_DESC_F_WRITE;
250 uint16_t head = q->last % q->qsz; /* `last` record next writable desc entry for request */
258 q->desc[head].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)req));
259 q->desc[head].len = reqSize;
452 q->desc[i].flag = VIRTQ_DESC_F_NEXT;
453 q->desc[i].next = i + 1;
454 q->desc[i + 1].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)&g_virtGpu->resp));
455 q->desc[i + 1].len = sizeof(g_virtGpu->resp);
456 q->desc[i + 1].flag = VIRTQ_DESC_F_WRITE;