Lines Matching defs:port
37 struct UartPl011Port *port = NULL;
45 port = (struct UartPl011Port *)udd->private;
46 status = OSAL_READW(port->physBase + UART_MIS);
49 fr = OSAL_READB(port->physBase + UART_FR);
53 buf[count++] = OSAL_READB(port->physBase + UART_DR);
65 OSAL_WRITEW(0xFFFF, port->physBase + UART_CLR);
69 static void Pl011ConfigBaudrate(const struct UartDriverData *udd, const struct UartPl011Port *port)
88 OSAL_WRITEL(divider, port->physBase + UART_IBRD);
89 OSAL_WRITEL(fraction, port->physBase + UART_FBRD);
158 static void Pl011ConfigLCRH(const struct UartDriverData *udd, const struct UartPl011Port *port, uint32_t lcrh)
169 OSAL_WRITEB(lcrh, port->physBase + UART_LCR_H);
176 struct UartPl011Port *port = NULL;
178 port = (struct UartPl011Port *)udd->private;
179 if (port == NULL) {
180 HDF_LOGE("%s: port is NULL", __func__);
184 cr = OSAL_READW(port->physBase + UART_CR);
186 lcrh = OSAL_READW(port->physBase + UART_LCR_H);
188 OSAL_WRITEW(0, port->physBase + UART_CR);
201 OSAL_WRITEB(lcrh, port->physBase + UART_LCR_H);
204 OSAL_WRITEW(cr, port->physBase + UART_CR);
207 Pl011ConfigBaudrate(udd, port);
210 Pl011ConfigLCRH(udd, port, lcrh);
214 OSAL_WRITEW(cr, port->physBase + UART_CR);
222 struct UartPl011Port *port = NULL;
228 port = (struct UartPl011Port *)udd->private;
229 if (port == NULL) {
230 HDF_LOGE("%s: port is null", __func__);
238 OSAL_WRITEW(0, port->physBase + UART_CR);
239 OSAL_WRITEW(0xFF, port->physBase + UART_RSR);
241 OSAL_WRITEW(0xFFFF, port->physBase + UART_CLR);
243 OSAL_WRITEW(0x0, port->physBase + UART_IMSC);
245 OSAL_WRITEW(UART_IFLS_RX4_8 | UART_IFLS_TX7_8, port->physBase + UART_IFLS);
247 if (!(port->flags & PL011_FLG_IRQ_REQUESTED)) {
248 ret = OsalRegisterIrq(port->irqNum, 0, Pl011Irq, "uart_pl011", udd);
250 port->flags |= PL011_FLG_IRQ_REQUESTED;
252 OSAL_WRITEW(UART_IMSC_RX | UART_IMSC_TIMEOUT, port->physBase + UART_IMSC);
256 cr = OSAL_READW(port->physBase + UART_CR);
258 OSAL_WRITEL(cr, port->physBase + UART_CR);
266 struct UartPl011Port *port = NULL;
272 port = (struct UartPl011Port *)udd->private;
273 if (port == NULL) {
274 HDF_LOGE("%s: port is null", __func__);
277 OSAL_WRITEW(0, port->physBase + UART_IMSC);
278 OSAL_WRITEW(0xFFFF, port->physBase + UART_CLR);
279 if (port->flags & PL011_FLG_IRQ_REQUESTED) {
280 OsalUnregisterIrq(port->irqNum, udd);
281 port->flags &= ~PL011_FLG_IRQ_REQUESTED;
284 reg_tmp = OSAL_READW(port->physBase + UART_CR);
288 OSAL_WRITEW(reg_tmp, port->physBase + UART_CR);
291 reg_tmp = OSAL_READW(port->physBase + UART_LCR_H);
294 OSAL_WRITEW(reg_tmp, port->physBase + UART_LCR_H);
305 struct UartPl011Port *port = NULL;
311 port = (struct UartPl011Port *)udd->private;
312 if (port == NULL) {
313 HDF_LOGE("%s: port is null", __func__);
317 (void)UartPutsReg(port->physBase, buf, count, UART_WITH_LOCK);
324 struct UartPl011Port *port = NULL;
330 port = (struct UartPl011Port *)udd->private;
331 if (port == NULL) {
332 HDF_LOGE("%s: port is null", __func__);
337 fr = OSAL_READB(port->physBase + UART_FR);