Lines Matching refs:regs
71 void DfxRegsRiscv64::SetFromFpMiniRegs(const uintptr_t* regs, const size_t size)
76 regsData_[REG_FP] = regs[0]; // 0 : fp offset
77 regsData_[REG_LR] = regs[1]; // 1 : lr offset
78 regsData_[REG_SP] = regs[2]; // 2 : sp offset
79 regsData_[REG_PC] = regs[3]; // 3 : pc offset
82 void DfxRegsRiscv64::SetFromQutMiniRegs(const uintptr_t* regs, const size_t size)
87 regsData_[REG_RISCV64_X20] = regs[1]; // 1 : X20 offset
88 regsData_[REG_RISCV64_X28] = regs[2]; // 2 : X28 offset
89 regsData_[REG_FP] = regs[3]; // 3 : fp offset
90 regsData_[REG_SP] = regs[4]; // 4 : sp offset
91 regsData_[REG_PC] = regs[5]; // 5 : pc offset
92 regsData_[REG_LR] = regs[6]; // 6 : lr offset
108 auto regs = GetRegsData();
111 regs[REG_RISCV64_X0], regs[REG_RISCV64_X1], regs[REG_RISCV64_X2], regs[REG_RISCV64_X3]);
114 regs[REG_RISCV64_X4], regs[REG_RISCV64_X5], regs[REG_RISCV64_X6], regs[REG_RISCV64_X7]);
117 regs[REG_RISCV64_X8], regs[REG_RISCV64_X9], regs[REG_RISCV64_X10], regs[REG_RISCV64_X11]);
120 regs[REG_RISCV64_X12], regs[REG_RISCV64_X13], regs[REG_RISCV64_X14], regs[REG_RISCV64_X15]);
123 regs[REG_RISCV64_X16], regs[REG_RISCV64_X17], regs[REG_RISCV64_X18], regs[REG_RISCV64_X19]);
126 regs[REG_RISCV64_X20], regs[REG_RISCV64_X21], regs[REG_RISCV64_X22], regs[REG_RISCV64_X23]);
129 regs[REG_RISCV64_X24], regs[REG_RISCV64_X25], regs[REG_RISCV64_X26], regs[REG_RISCV64_X27]);
132 regs[REG_RISCV64_X28], regs[REG_RISCV64_X29]);
135 regs[REG_RISCV64_X30], regs[REG_SP], regs[REG_PC]);