Lines Matching refs:circuit
31 bool Verifier::RunDataIntegrityCheck(const Circuit *circuit)
40 GateRef gate = circuit->GetGateRef(
42 reinterpret_cast<const Out *>(circuit->LoadGatePtrConst(GateRef(out)))->GetGateConst());
44 gate >= static_cast<int64_t>(circuit->GetCircuitDataSize())) {
54 reinterpret_cast<const Out *>(circuit->LoadGatePtrConst(GateRef(out)))->GetIndex() + 1);
55 if (out == circuit->GetCircuitDataSize()) {
58 if (out > circuit->GetCircuitDataSize() || out < 0) {
65 for (size_t idx = 0; idx < circuit->LoadGatePtrConst(gate)->GetNumIns(); idx++) {
66 const In *curIn = circuit->LoadGatePtrConst(gate)->GetInConst(idx);
67 if (!(circuit->GetSpaceDataStartPtrConst() < curIn && curIn < circuit->GetSpaceDataEndPtrConst())) {
69 LOG_COMPILER(ERROR) << "id: " << std::dec << circuit->GetId(gate);
72 if (gatesSet.count(circuit->GetGateRef(curIn->GetGateConst())) == 0) {
74 LOG_COMPILER(ERROR) << "id: " << std::dec << circuit->GetId(gate);
79 const Gate *curGate = circuit->LoadGatePtrConst(gate);
82 if (!(circuit->GetSpaceDataStartPtrConst() < curOut && curOut < circuit->GetSpaceDataEndPtrConst())) {
84 LOG_COMPILER(ERROR) << "id: " << std::dec << circuit->GetId(gate);
87 if (gatesSet.count(circuit->GetGateRef(curOut->GetGateConst())) == 0) {
89 LOG_COMPILER(ERROR) << "id: " << std::dec << circuit->GetId(gate);
94 if (!(circuit->GetSpaceDataStartPtrConst() < curOut &&
95 curOut < circuit->GetSpaceDataEndPtrConst())) {
97 LOG_COMPILER(ERROR) << "id: " << std::dec << circuit->GetId(gate);
100 if (gatesSet.count(circuit->GetGateRef(curOut->GetGateConst())) == 0) {
102 LOG_COMPILER(ERROR) << "id: " << std::dec << circuit->GetId(gate);
112 bool Verifier::RunStateGatesCheck(const Circuit *circuit, const std::vector<GateRef> &bbGatesList,
116 circuit->Verify(bbGate, methodName);
121 bool Verifier::RunCFGSoundnessCheck(const Circuit *circuit, const std::vector<GateRef> &bbGatesList,
125 GateAccessor gateAcc(const_cast<Circuit *>(circuit));
127 if (gateAcc.IsState(predGate) || circuit->GetOpCode(predGate) == OpCode::STATE_ENTRY) {
131 LOG_COMPILER(ERROR) << "(id=" << circuit->GetId(predGate) << ") is pred of "
132 << "(id=" << circuit->GetId(bbGate) << ")";
133 LOG_COMPILER(ERROR) << "(id=" << circuit->GetId(bbGate) << ") is reachable from entry";
134 LOG_COMPILER(ERROR) << "(id=" << circuit->GetId(predGate) << ") is unreachable from entry";
143 bool Verifier::RunCFGIsDAGCheck(const Circuit *circuit)
145 circuit->AdvanceTime();
152 GateAccessor gateAcc(const_cast<Circuit *>(circuit));
191 bool Verifier::RunCFGReducibilityCheck(const Circuit *circuit, const std::vector<GateRef> &bbGatesList,
196 if (circuit->GetOpCode(curGate) == OpCode::LOOP_BACK) {
197 GateAccessor gateAcc(const_cast<Circuit *>(circuit));
200 if (use.GetIndex() >= circuit->LoadGatePtrConst(*use)->GetStateCount()) {
208 LOG_COMPILER(ERROR) << "(id=" << circuit->GetId(*use) << ") is loop back succ of "
209 << "(id=" << circuit->GetId(curGate) << ")";
210 LOG_COMPILER(ERROR) << "(id=" << circuit->GetId(*use) << ") does not dominate "
211 << "(id=" << circuit->GetId(curGate) << ")";
220 bool Verifier::RunFixedGatesCheck(const Circuit *circuit, const std::vector<GateRef> &fixedGatesList)
223 circuit->Verify(fixedGate);
228 bool Verifier::RunFixedGatesRelationsCheck(const Circuit *circuit, const std::vector<GateRef> &fixedGatesList,
232 ConstGateAccessor ac(circuit);
240 (circuit->GetOpCode(circuit->GetIn(fixedGate, 0)) == OpCode::LOOP_BEGIN && cnt == 2)) {
242 auto a = bbGatesAddrToIdx.at(circuit->GetIn(predGate, 0));
243 auto b = bbGatesAddrToIdx.at(circuit->GetIn(circuit->GetIn(fixedGate, 0),
249 << circuit->GetId(predGate)
251 << circuit->GetId(fixedGate) << ")";
252 LOG_COMPILER(ERROR) << "BB_" << bbGatesAddrToIdx.at(circuit->GetIn(predGate, 0))
254 << bbGatesAddrToIdx.at(circuit->GetIn(circuit->GetIn(fixedGate, 0),
265 bool Verifier::RunFlowCyclesFind(const Circuit *circuit, std::vector<GateRef> *schedulableGatesListPtr,
268 circuit->AdvanceTime();
269 ConstGateAccessor ac(circuit);
276 if (circuit->GetMark(predGate) == MarkCode::NO_MARK) {
278 circuit->SetMark(predGate, MarkCode::VISITED);
288 if (circuit->GetMark(predGate) == MarkCode::NO_MARK) {
290 circuit->SetMark(predGate, MarkCode::VISITED);
295 circuit->AdvanceTime();
296 GateAccessor gateAcc(const_cast<Circuit *>(circuit));
329 LOG_COMPILER(ERROR) << "(id=" << circuit->GetId(prev) << ") is prev of "
330 << "(id=" << circuit->GetId(cur) << ")";
331 LOG_COMPILER(ERROR) << "(id=" << circuit->GetId(prev) << ") is reachable from "
332 << "(id=" << circuit->GetId(cur) << ") without passing selectors";
361 bool Verifier::RunSchedulableGatesCheck(const Circuit *circuit, const std::vector<GateRef> &schedulableGatesList)
364 circuit->Verify(schedulableGate);
369 bool Verifier::RunPrologGatesCheck(const Circuit *circuit, const std::vector<GateRef> &schedulableGatesList)
371 ConstGateAccessor ac(circuit);
377 circuit->Verify(r);
384 bool Verifier::RunSchedulingBoundsCheck(const Circuit *circuit,
393 if (!Scheduler::CalculateSchedulingUpperBound(circuit, bbGatesAddrToIdx, isAncestor,
401 Scheduler::CalculateSchedulingLowerBound(circuit, bbGatesAddrToIdx, lowestCommonAncestor, lowerBound);
409 << circuit->GetId(item.first) << ") is not consistent";
420 void Verifier::FindFixedGates(const Circuit *circuit, const std::vector<GateRef> &bbGatesList,
423 ConstGateAccessor ac(circuit);
425 for (const auto &succGate : circuit->GetOutVector(bbGate)) {
433 bool Verifier::RunFlowCyclesFind(const Circuit* circuit)
435 GateAccessor acc(const_cast<Circuit *>(circuit));
436 circuit->AdvanceTime();
479 bool Verifier::Run(const Circuit *circuit, const std::string& methodName, bool enableLog)
481 if (!RunDataIntegrityCheck(circuit)) {
490 Scheduler::CalculateDominatorTree(circuit, bbGatesList, bbGatesAddrToIdx, immDom);
491 if (!RunStateGatesCheck(circuit, bbGatesList, methodName)) {
497 if (!RunCFGSoundnessCheck(circuit, bbGatesList, bbGatesAddrToIdx)) {
503 if (!RunCFGIsDAGCheck(circuit)) {
572 if (!RunCFGReducibilityCheck(circuit, bbGatesList, bbGatesAddrToIdx, isAncestor)) {
579 FindFixedGates(circuit, bbGatesList, fixedGatesList);
580 if (!RunFixedGatesCheck(circuit, fixedGatesList)) {
586 if (!RunFixedGatesRelationsCheck(circuit, fixedGatesList, bbGatesAddrToIdx, isAncestor)) {
593 if (!RunFlowCyclesFind(circuit, &schedulableGatesList, bbGatesList, fixedGatesList)) {
599 if (!RunSchedulableGatesCheck(circuit, fixedGatesList)) {
605 if (!RunPrologGatesCheck(circuit, fixedGatesList)) {
611 if (!RunSchedulingBoundsCheck(circuit, schedulableGatesList, bbGatesAddrToIdx, isAncestor, lowestCommonAncestor)) {