Lines Matching refs:bbGatesAddrToIdx
46 std::unordered_map<GateRef, size_t> &bbGatesAddrToIdx,
77 bbGatesAddrToIdx[bbGatesList[idx]] = idx;
99 if (bbGatesAddrToIdx.count(predGate) > 0) {
100 size_t preGateIdx = bbGatesAddrToIdx[predGate];
135 std::unordered_map<GateRef, size_t> bbGatesAddrToIdx;
137 Scheduler::CalculateDominatorTree(circuit, bbGatesList, bbGatesAddrToIdx, immDom);
210 Scheduler::CalculateSchedulingLowerBound(circuit, bbGatesAddrToIdx, lowestCommonAncestor, lowerBound, &order);
227 result[bbGatesAddrToIdx.at(acc.GetIn(succGate, 0))].push_back(succGate);
238 const std::unordered_map<GateRef, size_t> &bbGatesAddrToIdx,
262 returnValue = bbGatesAddrToIdx.at(acc.GetIn(gate, 0));
265 returnValue = bbGatesAddrToIdx.at(gate);
344 const std::unordered_map<GateRef, size_t> &bbGatesAddrToIdx,
348 for (const auto &item : bbGatesAddrToIdx) {
361 const std::unordered_map<GateRef, size_t> &bbGatesAddrToIdx,
368 CalculateFixedGatesList(circuit, bbGatesAddrToIdx, bbAndFixedGatesList);
434 curLowerBound = bbGatesAddrToIdx.at(curGate);
437 curLowerBound = bbGatesAddrToIdx.at(acc.GetIn(acc.GetIn(curGate, 0), idx - 1));
440 curLowerBound = bbGatesAddrToIdx.at(acc.GetIn(curGate, 0));
468 std::unordered_map<GateRef, size_t> bbGatesAddrToIdx;
470 Scheduler::CalculateDominatorTree(circuit, bbGatesList, bbGatesAddrToIdx, immDom);
484 LOG_COMPILER(INFO) << (isFirst ? "" : " ") << bbGatesAddrToIdx.at(predState);
496 LOG_COMPILER(INFO) << (isFirst ? "" : " ") << bbGatesAddrToIdx.at(succState);