Lines Matching defs:instIdx
48 size_t instIdx = 0;
49 while (instIdx < instNum) {
51 GateRef current = currentBB[instIdx];
56 needRetraverse = VisitHeapAlloc(current, cfg, bbIdx, instIdx);
60 needRetraverse = VisitStore(current, cfg, bbIdx, instIdx);
69 instIdx = needRetraverse ? 0 : (instIdx + 1);
76 bool PostSchedule::VisitHeapAlloc(GateRef gate, ControlFlowGraph &cfg, size_t bbIdx, size_t instIdx)
89 ReplaceGateDirectly(currentBBGates, cfg, bbIdx, instIdx);
95 ReplaceGateDirectly(currentBBGates, cfg, bbIdx, instIdx);
99 ScheduleEndBB(endBBGates, cfg, bbIdx, instIdx);
102 ScheduleCurrentBB(currentBBGates, cfg, bbIdx, instIdx);
107 void PostSchedule::ReplaceGateDirectly(std::vector<GateRef> &gates, ControlFlowGraph &cfg, size_t bbIdx, size_t instIdx)
110 bb.insert(bb.begin() + instIdx, gates.begin(), gates.end());
111 bb.erase(bb.begin() + instIdx + gates.size());
114 void PostSchedule::ScheduleEndBB(std::vector<GateRef> &gates, ControlFlowGraph &cfg, size_t bbIdx, size_t instIdx)
117 if (instIdx > 0) {
118 gates.insert(gates.begin() + 1, bb.begin(), bb.begin() + instIdx); // 1: after state gate
131 size_t instIdx)
134 if (instIdx == 0) {
137 bb.erase(bb.begin(), bb.begin() + instIdx + 1); // 1: include current gate
369 bool PostSchedule::VisitStore(GateRef gate, ControlFlowGraph &cfg, size_t bbIdx, size_t instIdx)
379 ScheduleEndBB(endBBGates, cfg, bbIdx, instIdx);
381 ScheduleCurrentBB(currentBBGates, cfg, bbIdx, instIdx);
386 ReplaceGateDirectly(currentBBGates, cfg, bbIdx, instIdx);
391 ReplaceGateDirectly(currentBBGates, cfg, bbIdx, instIdx);
590 for (size_t instIdx = 0; instIdx < bb.size(); instIdx++) {
591 GateRef gate = bb[instIdx];