Lines Matching refs:imm
28 LogicalImmediate LogicalImmediate::Create(uint64_t imm, int width)
30 if ((imm == 0ULL) || (imm == ~0ULL) ||
31 ((width != RegXSize) && (((imm >> width) != 0) || (imm == (~0ULL >> (RegXSize - width)))))) {
41 if ((imm & mask) != ((imm >> size) & mask)) {
51 imm &= mask;
53 if (IsShiftedMask_64(imm)) {
54 i = CountTrailingZeros64(imm);
56 cto = CountTrailingOnes64(imm >> i);
58 imm |= ~mask;
59 if (!IsShiftedMask_64(~imm)) {
63 uint32_t clo = CountLeadingOnes64(imm);
65 cto = clo + CountTrailingOnes64(imm) - (static_cast<uint32_t>(RegXSize) - size);
109 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
111 imm >>= 3; // 3: 64 RegSise, imm/8 to remove trailing zeros
113 imm >>= 2; // 2: 32 RegSise, imm/4 to remove trailing zeros
115 uint32_t instructionCode = Sf(sf) | op | LoadAndStorePairImm(imm) | Rt2(rt2.GetId()) |
143 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
145 imm >>= 3; // 3: 64 RegSise, imm/8 to remove trailing zeros
147 imm >>= 2; // 2: 32 RegSise, imm/4 to remove trailing zeros
149 uint32_t instructionCode = Sf(sf) | op | LoadAndStorePairImm(imm) | Rt2(rt2.GetId()) |
176 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
180 imm >>= 2;
184 imm >>= 3;
188 imm >>= 4;
195 uint32_t instructionCode = opc | op | LoadAndStorePairImm(imm) | Rt2(vt2.GetId()) |
222 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
226 imm >>= 2;
230 imm >>= 3;
234 imm >>= 4;
241 uint32_t instructionCode = opc | op | LoadAndStorePairImm(imm) | Rt2(vt2.GetId()) |
282 uint64_t imm = GetImmOfLdr(operand, scale, regX);
285 uint32_t instructionCode = ((regX && (scale == Scale::Q)) << 30) | op | LoadAndStoreImm(imm, isSigned) |
325 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
331 imm >>= 3; // 3: 64 RegSise, imm/8 to remove trailing zeros
333 imm >>= 2; // 2: 32 RegSise, imm/4 to remove trailing zeros
348 uint32_t instructionCode = (regX << 30) | op | LoadAndStoreImm(imm, isSigned) |
362 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
364 uint32_t instructionCode = (regX << 30) | op | LoadAndStoreImm(imm, true) |
374 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
376 uint32_t instructionCode = (regX << 30) | op | LoadAndStoreImm(imm, true) |
381 void AssemblerAarch64::Mov(const Register &rd, const Immediate &imm)
385 uint64_t immValue = static_cast<uint64_t>(imm.Value());
491 static uint64_t UpdateImm(uint64_t imm, unsigned idx, bool clear)
495 imm &= ~(HWORD_MASK << idx);
498 imm |= HWORD_MASK << idx;
500 return imm;
503 bool AssemblerAarch64::TrySequenceOfOnes(const Register &rd, uint64_t imm)
510 int64_t himm = (imm >> shift) & HWORD_MASK;
538 uint64_t orrImm = imm;
542 uint64_t himm = (imm >> shift) & HWORD_MASK;
563 Movk(rd, (imm >> firstMovkShift) & HWORD_MASK, firstMovkShift);
565 Movk(rd, (imm >> secondMovkShift) & HWORD_MASK, secondMovkShift);
570 bool AssemblerAarch64::TryReplicateHWords(const Register &rd, uint64_t imm)
575 uint64_t halfWord = (imm >> idx) & HWORD_MASK;
596 imm16 = (imm >> shift) & HWORD_MASK;
609 imm16 = (imm >> shift) & HWORD_MASK;
620 void AssemblerAarch64::EmitMovInstruct(const Register &rd, uint64_t imm,
626 imm = ~imm;
630 if (imm != 0) {
631 int lz = static_cast<int>(CountLeadingZeros64(imm));
632 int tz = static_cast<int>(CountTrailingZeros64(imm));
637 uint64_t imm16 = (imm >> firstshift) & HWORD_MASK;
640 imm = ~imm;
649 imm16 = (imm >> firstshift) & HWORD_MASK;
658 void AssemblerAarch64::Movz(const Register &rd, uint64_t imm, int shift)
660 MovWide(MoveOpCode::MOVZ, rd, imm, shift);
663 void AssemblerAarch64::Movk(const Register &rd, uint64_t imm, int shift)
665 MovWide(MoveOpCode::MOVK, rd, imm, shift);
668 void AssemblerAarch64::Movn(const Register &rd, uint64_t imm, int shift)
670 MovWide(MoveOpCode::MOVN, rd, imm, shift);
673 void AssemblerAarch64::MovWide(uint32_t op, const Register &rd, uint64_t imm, int shift)
675 uint32_t imm_field = (imm << MOV_WIDE_Imm16_LOWBITS) & MOV_WIDE_Imm16_MASK;
682 void AssemblerAarch64::Orr(const Register &rd, const Register &rn, const LogicalImmediate &imm)
684 BitWiseOpImm(ORR_Imm, rd, rn, imm.Value());
687 void AssemblerAarch64::And(const Register &rd, const Register &rn, const LogicalImmediate &imm)
689 BitWiseOpImm(AND_Imm, rd, rn, imm.Value());
692 void AssemblerAarch64::Ands(const Register &rd, const Register &rn, const LogicalImmediate &imm)
694 BitWiseOpImm(ANDS_Imm, rd, rn, imm.Value());
715 void AssemblerAarch64::BitWiseOpImm(BitwiseOpCode op, const Register &rd, const Register &rn, uint64_t imm)
717 uint32_t code = Sf(!rd.IsW()) | op | imm | Rn(rn.GetId()) | Rd(rd.GetId());
780 int64_t imm = static_cast<int64_t>(operand.ImmediateValue());
781 if (imm < 0) {
782 AddSubImm(SUB_Imm, rd, rn, false, -1 * imm);
784 AddSubImm(ADD_Imm, rd, rn, false, imm);
811 int64_t imm = static_cast<int64_t>(operand.ImmediateValue());
812 if (imm < 0) {
813 AddSubImm(ADD_Imm, rd, rn, false, -1 * imm);
815 AddSubImm(SUB_Imm, rd, rn, false, imm);
839 bool AssemblerAarch64::IsAddSubImm(uint64_t imm)
842 if (imm <= IMM12_MASK) {
846 if (((imm & IMM12_MASK) == 0) && ((imm & ~IMM12_MASK) <= IMM12_MASK)) {
852 void AssemblerAarch64::AddSubImm(AddSubOpCode op, const Register &rd, const Register &rn, bool setFlags, uint64_t imm)
854 ASSERT(IsAddSubImm(imm));
857 uint64_t imm12 = imm & (~IMM12_MASK);
861 imm12 = imm;
913 void AssemblerAarch64::B(int32_t imm)
915 uint32_t code = BranchOpCode::Branch | ((imm << BRANCH_Imm26_LOWBITS) & BRANCH_Imm26_MASK);
933 void AssemblerAarch64::Bl(int32_t imm)
935 uint32_t code = CallOpCode::BL | ((imm << BRANCH_Imm26_LOWBITS) & BRANCH_Imm26_MASK);
954 void AssemblerAarch64::B(Condition cond, int32_t imm)
956 uint32_t code = BranchOpCode::BranchCond | BranchImm19(imm) | cond;
976 void AssemblerAarch64::Cbz(const Register &rt, int32_t imm)
978 uint32_t code = Sf(!rt.IsW()) | BranchOpCode::CBZ | BranchImm19(imm) | rt.GetId();
982 void AssemblerAarch64::Cbnz(const Register &rt, int32_t imm)
984 uint32_t code = Sf(!rt.IsW()) | BranchOpCode::CBNZ | BranchImm19(imm) | rt.GetId();
996 void AssemblerAarch64::Tbz(const Register &rt, int32_t bitPos, int32_t imm)
1000 uint32_t imm14 = (imm << BRANCH_Imm14_LOWBITS) & BRANCH_Imm14_MASK;
1013 void AssemblerAarch64::Tbnz(const Register &rt, int32_t bitPos, int32_t imm)
1017 uint32_t imm14 = (imm <<BRANCH_Imm14_LOWBITS) & BRANCH_Imm14_MASK;
1027 void AssemblerAarch64::Tst(const Register &rn, const LogicalImmediate &imm)
1029 Ands(Register(Zero, rn.GetType()), rn, imm);
1141 void AssemblerAarch64::Brk(const Immediate &imm)
1144 (static_cast<uint32_t>(imm.Value()) << BRK_Imm16_LOWBITS) & BRK_Imm16_MASK;
1152 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
1155 imm >>= 1;
1158 imm >>= 3; // 3: 64 RegSise, imm/8 to remove trailing zeros
1160 imm >>= 2; // 2: 32 RegSise, imm/4 to remove trailing zeros
1164 return imm;