Lines Matching defs:rn
292 Register rn = operand.GetRegBase();
298 extendField | shiftField | Rn(rn.GetId()) | Rt(rt.GetId());
682 void AssemblerAarch64::Orr(const Register &rd, const Register &rn, const LogicalImmediate &imm)
684 BitWiseOpImm(ORR_Imm, rd, rn, imm.Value());
687 void AssemblerAarch64::And(const Register &rd, const Register &rn, const LogicalImmediate &imm)
689 BitWiseOpImm(AND_Imm, rd, rn, imm.Value());
692 void AssemblerAarch64::Ands(const Register &rd, const Register &rn, const LogicalImmediate &imm)
694 BitWiseOpImm(ANDS_Imm, rd, rn, imm.Value());
697 void AssemblerAarch64::Orr(const Register &rd, const Register &rn, const Operand &operand)
700 BitWiseOpShift(ORR_Shift, rd, rn, operand);
703 void AssemblerAarch64::And(const Register &rd, const Register &rn, const Operand &operand)
706 BitWiseOpShift(AND_Shift, rd, rn, operand);
709 void AssemblerAarch64::Ands(const Register &rd, const Register &rn, const Operand &operand)
712 BitWiseOpShift(ANDS_Shift, rd, rn, operand);
715 void AssemblerAarch64::BitWiseOpImm(BitwiseOpCode op, const Register &rd, const Register &rn, uint64_t imm)
717 uint32_t code = Sf(!rd.IsW()) | op | imm | Rn(rn.GetId()) | Rd(rd.GetId());
721 void AssemblerAarch64::BitWiseOpShift(BitwiseOpCode op, const Register &rd, const Register &rn, const Operand &operand)
726 shift_amount | Rn(rn.GetId()) | Rd(rd.GetId());
730 void AssemblerAarch64::Lsl(const Register &rd, const Register &rn, const Register &rm)
732 uint32_t code = Sf(!rd.IsW()) | LSL_Reg | Rm(rm.GetId()) | Rn(rn.GetId()) | Rd(rd.GetId());
736 void AssemblerAarch64::Lsr(const Register &rd, const Register &rn, const Register &rm)
738 uint32_t code = Sf(!rd.IsW()) | LSR_Reg | Rm(rm.GetId()) | Rn(rn.GetId()) | Rd(rd.GetId());
742 void AssemblerAarch64::Ubfm(const Register &rd, const Register &rn, unsigned immr, unsigned imms)
748 uint32_t code = Sf(sf) | UBFM | n | immr_field | imms_field | Rn(rn.GetId()) | Rd(rd.GetId());
752 void AssemblerAarch64::Bfm(const Register &rd, const Register &rn, unsigned immr, unsigned imms)
758 uint32_t code = Sf(sf) | BFM | n | immr_field | imms_field | Rn(rn.GetId()) | Rd(rd.GetId());
762 void AssemblerAarch64::Lsr(const Register &rd, const Register &rn, unsigned shift)
774 Ubfm(rd, rn, shift, imms);
777 void AssemblerAarch64::Add(const Register &rd, const Register &rn, const Operand &operand)
782 AddSubImm(SUB_Imm, rd, rn, false, -1 * imm);
784 AddSubImm(ADD_Imm, rd, rn, false, imm);
788 AddSubReg(ADD_Shift, rd, rn, false, operand);
790 AddSubReg(ADD_Extend, rd, rn, false, operand);
795 void AssemblerAarch64::Adds(const Register &rd, const Register &rn, const Operand &operand)
798 AddSubImm(ADD_Imm, rd, rn, true, operand.ImmediateValue());
801 AddSubReg(ADD_Shift, rd, rn, true, operand);
803 AddSubReg(ADD_Extend, rd, rn, true, operand);
808 void AssemblerAarch64::Sub(const Register &rd, const Register &rn, const Operand &operand)
813 AddSubImm(ADD_Imm, rd, rn, false, -1 * imm);
815 AddSubImm(SUB_Imm, rd, rn, false, imm);
819 AddSubReg(SUB_Shift, rd, rn, false, operand);
821 AddSubReg(SUB_Extend, rd, rn, false, operand);
826 void AssemblerAarch64::Subs(const Register &rd, const Register &rn, const Operand &operand)
829 AddSubImm(SUB_Imm, rd, rn, true, operand.ImmediateValue());
832 AddSubReg(SUB_Shift, rd, rn, true, operand);
834 AddSubReg(SUB_Extend, rd, rn, true, operand);
852 void AssemblerAarch64::AddSubImm(AddSubOpCode op, const Register &rd, const Register &rn, bool setFlags, uint64_t imm)
866 uint32_t code = Sf(!rd.IsW()) | op | flags_field | shift_field | imm_field | Rd(rd.GetId()) | Rn(rn.GetId());
870 void AssemblerAarch64::AddSubReg(AddSubOpCode op, const Register &rd, const Register &rn,
880 shift_amount | Rn(rn.GetId()) | Rd(rd.GetId());
887 extend_shift | Rn(rn.GetId()) | Rd(rd.GetId());
897 void AssemblerAarch64::CMov(const Register &rd, const Register &rn, const Operand &operand, Condition cond)
901 uint32_t code = Sf(!rd.IsW()) | CSEL | Rm(operand.Reg().GetId()) | cond_field | Rn(rn.GetId()) | Rd(rd.GetId());
919 void AssemblerAarch64::Br(const Register &rn)
921 uint32_t code = BranchOpCode::BR | Rn(rn.GetId());
939 void AssemblerAarch64::Blr(const Register &rn)
941 ASSERT(!rn.IsW());
942 uint32_t code = CallOpCode::BLR | Rn(rn.GetId());
1022 void AssemblerAarch64::Tst(const Register& rn, const Operand& operand)
1024 Ands(Register(Zero, rn.GetType()), rn, operand);
1027 void AssemblerAarch64::Tst(const Register &rn, const LogicalImmediate &imm)
1029 Ands(Register(Zero, rn.GetType()), rn, imm);
1135 void AssemblerAarch64::Ret(const Register &rn)
1137 uint32_t code = RetOpCode::Ret | Rn(rn.GetId());