Lines Matching defs:operand
90 void AssemblerAarch64::Ldp(const Register &rt, const Register &rt2, const MemoryOperand &operand)
93 if (operand.IsImmediateOffset()) {
94 switch (operand.GetAddrMode()) {
109 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
116 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId());
124 void AssemblerAarch64::Stp(const Register &rt, const Register &rt2, const MemoryOperand &operand)
127 if (operand.IsImmediateOffset()) {
128 switch (operand.GetAddrMode()) {
143 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
150 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId());
158 void AssemblerAarch64::Ldp(const VectorRegister &vt, const VectorRegister &vt2, const MemoryOperand &operand)
161 if (operand.IsImmediateOffset()) {
162 switch (operand.GetAddrMode()) {
176 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
196 Rn(operand.GetRegBase().GetId()) | Rt(vt.GetId());
204 void AssemblerAarch64::Stp(const VectorRegister &vt, const VectorRegister &vt2, const MemoryOperand &operand)
207 if (operand.IsImmediateOffset()) {
208 switch (operand.GetAddrMode()) {
222 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
242 Rn(operand.GetRegBase().GetId()) | Rt(vt.GetId());
277 void AssemblerAarch64::Ldr(const Register &rt, const MemoryOperand &operand, Scale scale)
280 uint32_t op = GetOpcodeOfLdr(operand, scale);
281 if (operand.IsImmediateOffset()) {
282 uint64_t imm = GetImmOfLdr(operand, scale, regX);
283 bool isSigned = operand.GetAddrMode() != AddrMode::OFFSET;
286 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId());
289 ASSERT(operand.GetExtendOption() != Extend::NO_EXTEND);
290 uint32_t shift = GetShiftOfLdr(operand, scale, regX);
291 Register rm = operand.GetRegisterOffset();
292 Register rn = operand.GetRegBase();
294 (operand.GetExtendOption() << LDR_STR_Extend_LOWBITS) & LDR_STR_Extend_MASK;
303 void AssemblerAarch64::Ldr(const Register &rt, const MemoryOperand &operand)
305 Ldr(rt, operand, Scale::Q);
308 void AssemblerAarch64::Ldrh(const Register &rt, const MemoryOperand &operand)
311 Ldr(rt, operand, Scale::H);
314 void AssemblerAarch64::Ldrb(const Register &rt, const MemoryOperand &operand)
317 Ldr(rt, operand, Scale::B);
320 void AssemblerAarch64::Str(const Register &rt, const MemoryOperand &operand)
325 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
326 if (operand.IsImmediateOffset()) {
327 switch (operand.GetAddrMode()) {
349 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId());
357 void AssemblerAarch64::Ldur(const Register &rt, const MemoryOperand &operand)
361 ASSERT(operand.IsImmediateOffset());
362 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
365 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId());
369 void AssemblerAarch64::Stur(const Register &rt, const MemoryOperand &operand)
373 ASSERT(operand.IsImmediateOffset());
374 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
377 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId());
633 firstshift = (tz / 16) * 16; // 16 : 16 means the operand of MOVK/N/Z is 16 bits Immediate
635 lastshift = ((63 - lz) / 16) * 16; // 16 : 16 means the operand of MOVK/N/Z is 16 bits Immediate
648 firstshift += 16; // 16 : 16 means the operand of MOVK is 16 bits Immediate
697 void AssemblerAarch64::Orr(const Register &rd, const Register &rn, const Operand &operand)
699 ASSERT(operand.IsShifted());
700 BitWiseOpShift(ORR_Shift, rd, rn, operand);
703 void AssemblerAarch64::And(const Register &rd, const Register &rn, const Operand &operand)
705 ASSERT(operand.IsShifted());
706 BitWiseOpShift(AND_Shift, rd, rn, operand);
709 void AssemblerAarch64::Ands(const Register &rd, const Register &rn, const Operand &operand)
711 ASSERT(operand.IsShifted());
712 BitWiseOpShift(ANDS_Shift, rd, rn, operand);
721 void AssemblerAarch64::BitWiseOpShift(BitwiseOpCode op, const Register &rd, const Register &rn, const Operand &operand)
723 uint32_t shift_field = (operand.GetShiftOption() << BITWISE_OP_Shift_LOWBITS) & BITWISE_OP_Shift_MASK;
724 uint32_t shift_amount = (operand.GetShiftAmount() << BITWISE_OP_ShiftAmount_LOWBITS) & BITWISE_OP_ShiftAmount_MASK;
725 uint32_t code = Sf(!rd.IsW()) | op | shift_field | Rm(operand.Reg().GetId()) |
777 void AssemblerAarch64::Add(const Register &rd, const Register &rn, const Operand &operand)
779 if (operand.IsImmediate()) {
780 int64_t imm = static_cast<int64_t>(operand.ImmediateValue());
787 if (operand.IsShifted()) {
788 AddSubReg(ADD_Shift, rd, rn, false, operand);
790 AddSubReg(ADD_Extend, rd, rn, false, operand);
795 void AssemblerAarch64::Adds(const Register &rd, const Register &rn, const Operand &operand)
797 if (operand.IsImmediate()) {
798 AddSubImm(ADD_Imm, rd, rn, true, operand.ImmediateValue());
800 if (operand.IsShifted()) {
801 AddSubReg(ADD_Shift, rd, rn, true, operand);
803 AddSubReg(ADD_Extend, rd, rn, true, operand);
808 void AssemblerAarch64::Sub(const Register &rd, const Register &rn, const Operand &operand)
810 if (operand.IsImmediate()) {
811 int64_t imm = static_cast<int64_t>(operand.ImmediateValue());
818 if (operand.IsShifted()) {
819 AddSubReg(SUB_Shift, rd, rn, false, operand);
821 AddSubReg(SUB_Extend, rd, rn, false, operand);
826 void AssemblerAarch64::Subs(const Register &rd, const Register &rn, const Operand &operand)
828 if (operand.IsImmediate()) {
829 AddSubImm(SUB_Imm, rd, rn, true, operand.ImmediateValue());
831 if (operand.IsShifted()) {
832 AddSubReg(SUB_Shift, rd, rn, true, operand);
834 AddSubReg(SUB_Extend, rd, rn, true, operand);
871 bool setFlags, const Operand &operand)
875 if (operand.IsShifted()) {
876 uint32_t shift_field = ((operand.GetShiftOption()) << ADD_SUB_Shift_LOWBITS) & ADD_SUB_Shift_MASK;
877 uint32_t shift_amount = ((operand.GetShiftAmount()) << ADD_SUB_ShiftAmount_LOWBITS) & ADD_SUB_ShiftAmount_MASK;
879 code = Sf(!rd.IsW()) | op | flags_field | shift_field | Rm(operand.Reg().GetId()) |
884 (operand.GetExtendOption() << ADD_SUB_ExtendOption_LOWBITS) & ADD_SUB_ExtendOption_MASK;
885 uint32_t extend_shift = (operand.GetShiftAmount() << ADD_SUB_ExtendShift_LOWBITS) & ADD_SUB_ExtendShift_MASK;
886 code = Sf(!rd.IsW()) | op | flags_field | Rm(operand.Reg().GetId()) | extend_field |
892 void AssemblerAarch64::Cmp(const Register &rd, const Operand &operand)
894 Subs(Register(Zero, rd.GetType()), rd, operand);
897 void AssemblerAarch64::CMov(const Register &rd, const Register &rn, const Operand &operand, Condition cond)
899 ASSERT(!operand.IsImmediate());
901 uint32_t code = Sf(!rd.IsW()) | CSEL | Rm(operand.Reg().GetId()) | cond_field | Rn(rn.GetId()) | Rd(rd.GetId());
1022 void AssemblerAarch64::Tst(const Register& rn, const Operand& operand)
1024 Ands(Register(Zero, rn.GetType()), rn, operand);
1149 uint64_t AssemblerAarch64::GetImmOfLdr(const MemoryOperand &operand, Scale scale, bool isRegX)
1151 ASSERT(operand.IsImmediateOffset());
1152 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value());
1153 if (operand.GetAddrMode() == OFFSET) {
1167 uint64_t AssemblerAarch64::GetOpcodeOfLdr(const MemoryOperand &operand, Scale scale)
1170 if (operand.IsImmediateOffset()) {
1171 switch (operand.GetAddrMode()) {
1230 uint32_t AssemblerAarch64::GetShiftOfLdr(const MemoryOperand &operand, Scale scale, bool isRegX)
1234 shift = operand.GetShiftOption() != Shift::NO_SHIFT;
1236 shift = operand.GetShiftAmount();
1240 shift = operand.GetShiftAmount();